1 files changed, 31 insertions, 0 deletions
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v
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index 0000000..51977ac
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+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v
@@ -0,0 +1,31 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlconstant.v
+//--
+//--  Date          : 06/05/12
+//--
+//--  Description   : VERILOG description of a constant block.  This
+//--                  block does not use a core.
+//--
+//------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------
+//--
+//--  Module        : xlconstant
+//--
+//--  Architecture  : behavior
+//--
+//--  Description   : Top level VERILOG description of constant block
+//--
+//------------------------------------------------------------------------
+`timescale 1ps/1ps
+module xlconstant_v1_1_7_xlconstant (dout);
+	parameter CONST_VAL = 1;
+	parameter CONST_WIDTH = 1;
+	output [CONST_WIDTH-1:0] dout;
+
+	assign dout = CONST_VAL;
+endmodule
+
+