ip « design_1 « bd « sources_1 « pb_logique_seq.gen

Mode	Name	Size
d---------	design_1_M10_conversion_affichage_0	67	log plain
d---------	design_1_M2_fonction_distortion_dure1_0	71	log plain
d---------	design_1_M3_fonction_distorsion_dure2_0	71	log plain
d---------	design_1_M4_fonction3_0	55	log plain
d---------	design_1_M5_parametre_1_0	57	log plain
d---------	design_1_M6_parametre_2_0	57	log plain
d---------	design_1_M7_parametre_3_0	57	log plain
d---------	design_1_M8_commande_0	54	log plain
d---------	design_1_MEF_decodeur_i2s_0	59	log plain
d---------	design_1_Multiplexeur_choix_fonction_0	70	log plain
d---------	design_1_Multiplexeur_choix_parametre_0	71	log plain
d---------	design_1_affhexPmodSSD_v3_0_0	123	log plain
d---------	design_1_calcul_param_1_0_0	311	log plain
d---------	design_1_calcul_param_2_0_0	311	log plain
d---------	design_1_calcul_param_3_0_0	121	log plain
d---------	design_1_compteur_7bits_0	57	log plain
d---------	design_1_compteur_nbits_0_0	121	log plain
d---------	design_1_compteur_nbits_0_0_1	59	log plain
d---------	design_1_compteur_nbits_0_1	311	log plain
d---------	design_1_mef_cod_i2s_vsb_0_0	122	log plain
d---------	design_1_mef_cod_i2s_vsb_0_0_1	60	log plain
d---------	design_1_mef_decod_i2s_v1b_0_0	124	log plain
d---------	design_1_module_commande_0_0	122	log plain
d---------	design_1_mux2_0_0	271	log plain
d---------	design_1_mux2_0_0_1	49	log plain
d---------	design_1_mux4_0_0	111	log plain
d---------	design_1_mux4_0_1	111	log plain
d---------	design_1_parametre_0_0	54	log plain
d---------	design_1_reg_24b_0_0	114	log plain
d---------	design_1_reg_24b_0_1	114	log plain
d---------	design_1_reg_dec_24b_0_0	299	log plain
d---------	design_1_reg_dec_24b_fd_0_0	121	log plain
d---------	design_1_reg_dec_24b_fd_0_0_1	59	log plain
d---------	design_1_registre_24bits_droite_0	65	log plain
d---------	design_1_registre_24bits_gauche_0	65	log plain
d---------	design_1_registre_decalage_24bits_0	67	log plain
d---------	design_1_sig_fct_3_0_0	291	log plain
d---------	design_1_sig_fct_sat_dure_0_0	319	log plain
d---------	design_1_sig_fct_sat_dure_0_1	123	log plain
d---------	design_1_util_vector_logic_0_0	124	log plain
d---------	design_1_util_vector_logic_0_0_1	62	log plain
d---------	design_1_xlconcat_0_0	115	log plain
d---------	design_1_xlconcat_0_0_1	53	log plain
d---------	design_1_xlconstant_0_0	117	log plain
d---------	design_1_xlconstant_0_0_1	55	log plain
d---------	design_1_xlconstant_0_1	117	log plain
d---------	design_1_xlconstant_0_1_1	55	log plain
d---------	design_1_xlconstant_0_2	117	log plain
d---------	design_1_xlconstant_0_3	117	log plain
d---------	design_1_xlconstant_1_0	55	log plain
d---------	design_1_xlslice_0_0	114	log plain
d---------	design_1_xlslice_0_0_1	52	log plain