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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/23/2021 04:00:46 PM
-- Design Name:
-- Module Name: or2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity or2 is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
output : out STD_LOGIC);
end or2;
architecture Behavioral of or2 is
begin
output <= in1 or in2;
end Behavioral;
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