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authorBenjamin Chausse <benjamin@chausse.xyz>2025-05-03 12:52:42 -0400
committerBenjamin Chausse <benjamin@chausse.xyz>2025-05-03 12:52:42 -0400
commit1b8b70ea0d1f1dd79a1b1f1a1b05208bb8c1ca30 (patch)
tree3456dfab4f2864c098b1e0f64a320edacc2ae127 /pb_APP_log_comb.srcs/sources_1/imports
parentc92db53d3d503b86dc42328a359df6e0d4f549cc (diff)
Add4Bits works mothaflacka
Diffstat (limited to 'pb_APP_log_comb.srcs/sources_1/imports')
-rw-r--r--pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd13
1 files changed, 10 insertions, 3 deletions
diff --git a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
index 79209c9..b9be1dc 100644
--- a/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/imports/src/AppCombi_top.vhd
@@ -56,10 +56,10 @@ architecture BEHAVIORAL of AppCombi_top is
component Add4Bits is Port (
- A : in STD_LOGIC_VECTOR (0 to 3);
- B : in STD_LOGIC_VECTOR (0 to 3);
+ A : in STD_LOGIC_VECTOR (3 downto 0);
+ B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC;
- R : out STD_LOGIC_VECTOR (0 to 3);
+ R : out STD_LOGIC_VECTOR (3 downto 0);
Rc : out STD_LOGIC
);
end component;
@@ -114,6 +114,13 @@ begin
o_pmodled <= d_opa & d_opb; -- Les opérandes d'entrés reproduits combinés sur Pmod8LD
o_led (3 downto 0) <= '0' & '0' & '0' & d_S_1Hz; -- La LED0 sur la carte représente la retenue d'entrée
+adder4 : Add4Bits port map (
+ A => d_opa,
+ B => d_opb,
+ C => d_cin,
+ R => d_sum,
+ Rc => d_cout
+);
end BEHAVIORAL;