More linting and working vhdl_ls config

1 files changed, 9 insertions, 9 deletions

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
index 0b1ed7c..ca031bb 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
@@ -1,4 +1,4 @@
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- Company:
 -- Engineer:
 --
@@ -16,7 +16,7 @@
 -- Revision 0.01 - File Created
 -- Additional Comments:
 --
-----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 
 
 library IEEE;
@@ -31,19 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
-entity Add1BitA is
-    Port ( X : in STD_LOGIC;
-           Y : in STD_LOGIC;
-           Ci : in STD_LOGIC;
-           O : out STD_LOGIC;
-           Co : out STD_LOGIC);
+entity Add1BitA is Port (
+  X  : in  STD_LOGIC;
+  Y  : in  STD_LOGIC;
+  Ci : in  STD_LOGIC;
+  O  : out STD_LOGIC;
+  Co : out STD_LOGIC);
 end Add1BitA;
 
 architecture Behavioral of Add1BitA is
 
 begin
 
-  O <= (X xor Y) xor Ci;
+  O  <= (X xor Y) xor Ci;
   Co <= ((X xor Y) and Ci) or (X and Y);
 
 end;