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| author | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-05 10:52:25 -0400 |
|---|---|---|
| committer | Benjamin Chausse <benjamin@chausse.xyz> | 2025-05-05 10:52:25 -0400 |
| commit | 4bd43e9bd0dc5cb27df985bf171b77f3e1b6da21 (patch) | |
| tree | 1325b7d6aaccb003005945b6f5cae2cc7cc7d96b /pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd | |
| parent | 21c0053ad9597486a9a677fecb2e92dde80d38c2 (diff) | |
Minus_5 Testbench
Diffstat (limited to 'pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd')
| -rw-r--r-- | pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd b/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd index 977bac1..065bd1f 100644 --- a/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd +++ b/pb_APP_log_comb.srcs/sources_1/new/Moins_5.vhd @@ -31,9 +31,9 @@ use IEEE.STD_LOGIC_1164.ALL; --library UNISIM; --use UNISIM.VComponents.all; -entity Moins_5 is - Port ( Moins5 : out STD_LOGIC_VECTOR (3 downto 0); - ADCbin : in STD_LOGIC_VECTOR (3 downto 0)); +entity Moins_5 is Port ( + ADCbin : in STD_LOGIC_VECTOR (3 downto 0); + Moins5 : out STD_LOGIC_VECTOR (3 downto 0)); end Moins_5; |