unit test add 4 bit, Fix Add1bitB

3 files changed, 18 insertions, 16 deletions

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
index 5f99927..1d255c9 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
@@ -41,15 +41,14 @@ end Add1BitB;
 
 architecture Behavioral of Add1BitB is
 
-  signal buf: STD_LOGIC_VECTOR(2 downto 0);
-
 begin
 
 Adder: process(X, Y, Ci) is
+  variable buf: STD_LOGIC_VECTOR(2 downto 0);
 begin
-  buf(0) <= X;
-  buf(1) <= Y;
-  buf(2) <= Ci;
+  buf(0) := X;
+  buf(1) := Y;
+  buf(2) := Ci;
 
      case (buf) is
       when "000" =>
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
index 71c09d9..75c6cab 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -67,7 +67,7 @@ architecture Behavioral of Add4Bits is
 
 begin
 
-  first : Add1BitA port map (
+  first : Add1BitB port map (
     X  => A(0),
     Y  => B(0),
     Ci => C,
@@ -75,7 +75,7 @@ begin
     Co => bufA
   );
 
-  sec : Add1BitA port map (
+  sec : Add1BitB port map (
     X  => A(1),
     Y  => B(1),
     Ci => bufA,
@@ -83,7 +83,7 @@ begin
     Co => bufB
   );
 
-  third : Add1BitB port map (
+  third : Add1BitA port map (
     X  => A(2),
     Y  => B(2),
     Ci => bufB,
@@ -91,7 +91,7 @@ begin
     Co => bufC
   );
 
-  fourth : Add1BitB port map (
+  fourth : Add1BitA port map (
     X  => A(3),
     Y  => B(3),
     Ci => bufC,
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
index e0cb89c..470e7c4 100644
--- a/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
+++ b/pb_APP_log_comb.srcs/sources_1/new/Fct_2_3.vhd
@@ -35,13 +35,14 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 entity Fct_2_3 is
     Port ( ADCbin : in STD_LOGIC_VECTOR (3 downto 0);
-           A2_3 : out STD_LOGIC_VECTOR (2 downto 0));
+           A2_3 : out STD_LOGIC_VECTOR (3 downto 0));
 end Fct_2_3;
 
 architecture Behavioral of Fct_2_3 is
     signal shifted_once : STD_LOGIC_VECTOR(3 downto 0);
     signal shifted_twice : STD_LOGIC_VECTOR(3 downto 0);
     signal shifted_thrice : STD_LOGIC_VECTOR(3 downto 0);
+    signal carry_out : STD_LOGIC;
     
     component Add4Bits is
     Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
@@ -52,16 +53,18 @@ architecture Behavioral of Fct_2_3 is
     end component;
 begin
     -- N x 2^-1 : shifted once
-    shifted_once <= '0' & ADCbin(3 downto 0);
+    shifted_once <= '0' & ADCbin(3 downto 1);
 
     -- N x 2^-3 : shifted thrice
-    shifted_twice <= '0' & shifted_once(3 downto 0);
-    shifted_thrice <= '0' & shifted_twice(3 downto 0);
+    shifted_twice <= '0' & shifted_once(3 downto 1);
+    shifted_thrice <= '0' & shifted_twice(3 downto 1);
     
     -- Both are then added to give the result of the 2/3 multiplication (0.625)
     result : Add4Bits port map (
-        X  => shifted_once,
-        Y  => shifted_thrice,
-        O => A2_3
+        A  => "0110",
+        B  => "0001",
+        C => '0',
+        R => A2_3,
+        Rc => carry_out
     );
 end Behavioral;