Batman

4 files changed, 197 insertions, 0 deletions

diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
new file mode 100644
index 0000000..0b1ed7c
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitA.vhd
@@ -0,0 +1,49 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 04/30/2025 03:19:19 PM
+-- Design Name:
+-- Module Name: Add1BitA - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Add1BitA is
+    Port ( X : in STD_LOGIC;
+           Y : in STD_LOGIC;
+           Ci : in STD_LOGIC;
+           O : out STD_LOGIC;
+           Co : out STD_LOGIC);
+end Add1BitA;
+
+architecture Behavioral of Add1BitA is
+
+begin
+
+  O <= (X xor Y) xor Ci;
+  Co <= ((X xor Y) and Ci) or (X and Y);
+
+end;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
new file mode 100644
index 0000000..b00716e
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add1BitB.vhd
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/30/2025 03:19:19 PM
+-- Design Name: 
+-- Module Name: Add1BitB - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Add1BitB is
+    Port ( X : in STD_LOGIC;
+           Y : in STD_LOGIC;
+           Ci : in STD_LOGIC;
+           O : out STD_LOGIC;
+           Co : out STD_LOGIC);
+end Add1BitB;
+
+architecture Behavioral of Add1BitB is
+
+begin
+
+
+end Behavioral;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
new file mode 100644
index 0000000..be2cf13
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/Add4Bits.vhd
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/30/2025 03:19:19 PM
+-- Design Name: 
+-- Module Name: Add4Bits - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Add4Bits is
+    Port ( X : in STD_LOGIC_VECTOR (0 to 3);
+           Y : in STD_LOGIC_VECTOR (0 to 3);
+           Ci : in STD_LOGIC;
+           O : out STD_LOGIC_VECTOR (0 to 3);
+           Co : out STD_LOGIC);
+end Add4Bits;
+
+architecture Behavioral of Add4Bits is
+
+begin
+
+
+end Behavioral;
diff --git a/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd
new file mode 100644
index 0000000..7f5148d
--- /dev/null
+++ b/pb_APP_log_comb.srcs/sources_1/new/full_adder.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 04/30/2025 01:11:03 PM
+-- Design Name:
+-- Module Name: full_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity full_adder is
+    Port ( c_in : in STD_LOGIC;
+           a : in STD_LOGIC;
+           b : in STD_LOGIC;
+           o : out STD_LOGIC;
+           c_o : out STD_LOGIC);
+end full_adder;
+
+architecture Behavioral of full_adder is
+
+  signal aXb : STD_LOGIC;
+
+begin
+
+  aXb <= a xor b;
+
+  o <= aXb xor c_in;
+  c_o <= (aXb and c_in) or (a and b);
+
+
+end Behavioral;