Batman

27 files changed, 3155 insertions, 0 deletions

diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
new file mode 100644
index 0000000..0c61365
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_affhexPmodSSD_v3_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_affhexPmodSSD_v3_0_0;
+
+ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT affhexPmodSSD_v3 IS
+    GENERIC (
+      const_CLK_Hz : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT affhexPmodSSD_v3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : affhexPmodSSD_v3
+    GENERIC MAP (
+      const_CLK_Hz => 100000000
+    )
+    PORT MAP (
+      clk => clk,
+      reset => reset,
+      DA => DA,
+      i_btn => i_btn,
+      JPmod => JPmod
+    );
+END design_1_affhexPmodSSD_v3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
new file mode 100644
index 0000000..b90cd0b
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_1_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_1_0_0;
+
+ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_1 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_1;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_1
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_1_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
new file mode 100644
index 0000000..aeda442
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_2_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_2_0_0;
+
+ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_2 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_2
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_2_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
new file mode 100644
index 0000000..bc012a0
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_3_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_3_0_0;
+
+ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_3 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_3
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
new file mode 100644
index 0000000..c58480b
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_0;
+
+ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
new file mode 100644
index 0000000..efc345f
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_1 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_1;
+
+ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
new file mode 100644
index 0000000..9f669ea
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_cod_i2s_vsb_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_cod_i2s_vsb_0_0;
+
+ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_cod_i2s_vsb IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_cod_i2s_vsb;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_cod_i2s_vsb
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_cod_i2s_vsb_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
new file mode 100644
index 0000000..63454ae
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_decod_i2s_v1b_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_str_dat : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_decod_i2s_v1b_0_0;
+
+ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_decod_i2s_v1b IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_str_dat : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_decod_i2s_v1b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_decod_i2s_v1b
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_str_dat => o_str_dat,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_decod_i2s_v1b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
new file mode 100644
index 0000000..643d8ee
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
@@ -0,0 +1,109 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:module_commande:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_module_commande_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    o_reset : OUT STD_LOGIC;
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_module_commande_0_0;
+
+ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT module_commande IS
+    GENERIC (
+      nbtn : INTEGER;
+      mode_simulation : STD_LOGIC
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      o_reset : OUT STD_LOGIC;
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT module_commande;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : module_commande
+    GENERIC MAP (
+      nbtn => 4,
+      mode_simulation => '0'
+    )
+    PORT MAP (
+      clk => clk,
+      o_reset => o_reset,
+      i_btn => i_btn,
+      i_sw => i_sw,
+      o_btn_cd => o_btn_cd,
+      o_selection_fct => o_selection_fct,
+      o_selection_par => o_selection_par
+    );
+END design_1_module_commande_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
new file mode 100644
index 0000000..ffe2904
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
@@ -0,0 +1,92 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux2_0_0 IS
+  PORT (
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux2_0_0;
+
+ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux2 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux2
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      sel => sel,
+      input1 => input1,
+      input2 => input2,
+      output0 => output0
+    );
+END design_1_mux2_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
new file mode 100644
index 0000000..ae6ac28
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_0 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux4_0_0;
+
+ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
new file mode 100644
index 0000000..d30d1e5
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_1 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_mux4_0_1;
+
+ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 8
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
new file mode 100644
index 0000000..4ef9d64
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_0;
+
+ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
new file mode 100644
index 0000000..3883a48
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_1 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_1;
+
+ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
new file mode 100644
index 0000000..2dbb12a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
new file mode 100644
index 0000000..c8a9b85
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_fd_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_fd_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b_fd IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b_fd;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b_fd
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_fd_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
new file mode 100644
index 0000000..3a84972
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
@@ -0,0 +1,80 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_3_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_3_0_0;
+
+ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_3 IS
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_3
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
new file mode 100644
index 0000000..27c63d5
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_0;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"7FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
new file mode 100644
index 0000000..b557a37
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_1 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_1;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"1FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
new file mode 100644
index 0000000..c3f6299
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
@@ -0,0 +1,74 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_util_vector_logic_0_0 (
+  Op1,
+  Op2,
+  Res
+);
+
+input wire [0 : 0] Op1;
+input wire [0 : 0] Op2;
+output wire [0 : 0] Res;
+
+  util_vector_logic_v2_0_1_util_vector_logic #(
+    .C_OPERATION("or"),
+    .C_SIZE(1)
+  ) inst (
+    .Op1(Op1),
+    .Op2(Op2),
+    .Res(Res)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
new file mode 100644
index 0000000..25b5d97
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
@@ -0,0 +1,328 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconcat_0_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
new file mode 100644
index 0000000..a112873
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [7 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(8),
+    .CONST_VAL(8'H00)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
new file mode 100644
index 0000000..31c4f41
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_1 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
new file mode 100644
index 0000000..5011eda
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_2 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
new file mode 100644
index 0000000..65ddfe3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_3 (
+  dout
+);
+
+output wire [23 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(24),
+    .CONST_VAL(24'H000001)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
new file mode 100644
index 0000000..c5f22b1
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
@@ -0,0 +1,72 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlslice:1.0
+// IP Revision: 2
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlslice_0_0 (
+  Din,
+  Dout
+);
+
+input wire [23 : 0] Din;
+output wire [0 : 0] Dout;
+
+  xlslice_v1_0_2_xlslice #(
+    .DIN_WIDTH(24),
+    .DIN_FROM(23),
+    .DIN_TO(23)
+  ) inst (
+    .Din(Din),
+    .Dout(Dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd
new file mode 100644
index 0000000..4fbeb11
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd
@@ -0,0 +1,581 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Jan 16 11:48:36 2024
+--Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M1_decodeur_i2s_imp_17RYJKZ is
+  port (
+    clk : in STD_LOGIC;
+    i_data : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat_left : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat_right : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_str_dat : out STD_LOGIC
+  );
+end M1_decodeur_i2s_imp_17RYJKZ;
+
+architecture STRUCTURE of M1_decodeur_i2s_imp_17RYJKZ is
+  component design_1_compteur_nbits_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_0;
+  component design_1_mef_decod_i2s_v1b_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_str_dat : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_decod_i2s_v1b_0_0;
+  component design_1_reg_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_0;
+  component design_1_reg_24b_0_1 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_1;
+  component design_1_reg_dec_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_0_0;
+  component design_1_xlconstant_0_2 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_2;
+  component design_1_xlconstant_0_3 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_xlconstant_0_3;
+  signal clk_1 : STD_LOGIC;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_bit_enable : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_left : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_right : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_str_dat : STD_LOGIC;
+  signal reg_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_24b_1_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
+begin
+  clk_1 <= clk;
+  i_data_1 <= i_data;
+  i_lrc_1 <= i_lrc;
+  i_reset_1 <= i_reset;
+  o_dat_left(23 downto 0) <= reg_24b_1_o_dat(23 downto 0);
+  o_dat_right(23 downto 0) <= reg_24b_0_o_dat(23 downto 0);
+  o_str_dat <= mef_decod_i2s_v1b_0_o_str_dat;
+MEF_decodeur_i2s: component design_1_mef_decod_i2s_v1b_0_0
+     port map (
+      i_bclk => clk_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_bit_enable => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_cpt_bit_reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset,
+      o_load_left => mef_decod_i2s_v1b_0_o_load_left,
+      o_load_right => mef_decod_i2s_v1b_0_o_load_right,
+      o_str_dat => mef_decod_i2s_v1b_0_o_str_dat
+    );
+compteur_7bits: component design_1_compteur_nbits_0_0
+     port map (
+      clk => clk_1,
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset
+    );
+registre_24bits_droite: component design_1_reg_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_right,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_0_o_dat(23 downto 0)
+    );
+registre_24bits_gauche: component design_1_reg_24b_0_1
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_left,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_1_o_dat(23 downto 0)
+    );
+registre_decalage_24bits: component design_1_reg_dec_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat_bit => i_data_1,
+      i_dat_load(23 downto 0) => xlconstant_1_dout(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      i_load => xlconstant_0_dout(0),
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_2
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlconstant_1: component design_1_xlconstant_0_3
+     port map (
+      dout(23 downto 0) => xlconstant_1_dout(23 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M9_codeur_i2s_imp_1VJCTGL is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_dat_left : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_dat_right : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end M9_codeur_i2s_imp_1VJCTGL;
+
+architecture STRUCTURE of M9_codeur_i2s_imp_1VJCTGL is
+  component design_1_compteur_nbits_0_1 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_1;
+  component design_1_mef_cod_i2s_vsb_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_cod_i2s_vsb_0_0;
+  component design_1_mux2_0_0 is
+  port (
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux2_0_0;
+  component design_1_reg_dec_24b_fd_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_fd_0_0;
+  component design_1_util_vector_logic_0_0 is
+  port (
+    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_util_vector_logic_0_0;
+  component design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_xlconcat_0_0;
+  component design_1_xlconstant_0_1 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_1;
+  component design_1_xlslice_0_0 is
+  port (
+    Din : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlslice_0_0;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_bclk_0_1 : STD_LOGIC;
+  signal i_lrc_0_1 : STD_LOGIC;
+  signal i_reset_0_1 : STD_LOGIC;
+  signal input1_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal input2_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal mef_cod_i2s_vsb_0_o_bit_enable : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_left : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_right : STD_LOGIC;
+  signal mux2_0_output : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_fd_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  i_bclk_0_1 <= i_bclk;
+  i_lrc_0_1 <= i_lrc;
+  i_reset_0_1 <= i_reset;
+  input1_0_1(23 downto 0) <= i_dat_left(23 downto 0);
+  input2_0_1(23 downto 0) <= i_dat_right(23 downto 0);
+  o_dat(0) <= xlslice_0_Dout(0);
+compteur_nbits_0: component design_1_compteur_nbits_0_1
+     port map (
+      clk => i_bclk_0_1,
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset
+    );
+mef_cod_i2s_vsb_0: component design_1_mef_cod_i2s_vsb_0_0
+     port map (
+      i_bclk => i_bclk_0_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_0_1,
+      i_reset => i_reset_0_1,
+      o_bit_enable => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_cpt_bit_reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset,
+      o_load_left => mef_cod_i2s_vsb_0_o_load_left,
+      o_load_right => mef_cod_i2s_vsb_0_o_load_right
+    );
+mux2_0: component design_1_mux2_0_0
+     port map (
+      input1(23 downto 0) => input1_0_1(23 downto 0),
+      input2(23 downto 0) => input2_0_1(23 downto 0),
+      output0(23 downto 0) => mux2_0_output(23 downto 0),
+      sel(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+reg_dec_24b_fd_0: component design_1_reg_dec_24b_fd_0_0
+     port map (
+      i_clk => i_bclk_0_1,
+      i_dat_bit => xlconstant_0_dout(0),
+      i_dat_load(23 downto 0) => mux2_0_output(23 downto 0),
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      i_load => util_vector_logic_0_Res(0),
+      i_reset => i_reset_0_1,
+      o_dat(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0)
+    );
+util_vector_logic_0: component design_1_util_vector_logic_0_0
+     port map (
+      Op1(0) => mef_cod_i2s_vsb_0_o_load_left,
+      Op2(0) => mef_cod_i2s_vsb_0_o_load_right,
+      Res(0) => util_vector_logic_0_Res(0)
+    );
+xlconcat_0: component design_1_xlconcat_0_0
+     port map (
+      In0(0) => mef_cod_i2s_vsb_0_o_load_left,
+      In1(0) => mef_cod_i2s_vsb_0_o_load_right,
+      dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_1
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlslice_0: component design_1_xlslice_0_0
+     port map (
+      Din(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0),
+      Dout(0) => xlslice_0_Dout(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- Modules à modifier:
+  -- MEF_decodeur_i2s (dans M1_decodeur_i2s)
+  -- M5_parametre_1
+  -- M6_parametre_2
+  -- M8_commande
+  -- Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+  -- et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+  entity design_1 is
+  port (
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_recdat : in STD_LOGIC;
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=28,numReposBlks=26,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=19,numPkgbdBlks=0,bdsource=USER,""""""""""""""""""""""""""""""""""""""""""""""""""""da_clkrst_cnt""""""""""""""""""""""""""""""""""""""""""""""""""""=1,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_affhexPmodSSD_v3_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    DA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_affhexPmodSSD_v3_0_0;
+  component design_1_calcul_param_1_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_1_0_0;
+  component design_1_calcul_param_2_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_2_0_0;
+  component design_1_calcul_param_3_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_3_0_0;
+  component design_1_mux4_0_0 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux4_0_0;
+  component design_1_mux4_0_1 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_mux4_0_1;
+  component design_1_sig_fct_3_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_3_0_0;
+  component design_1_sig_fct_sat_dure_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_0;
+  component design_1_sig_fct_sat_dure_0_1 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_1;
+  component design_1_xlconstant_0_0 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_xlconstant_0_0;
+  component design_1_module_commande_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    o_reset : out STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_btn_cd : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_selection_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_selection_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_module_commande_0_0;
+  signal M10_conversion_affichage_JPmod : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal M8_commande_o_btn_cd : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal M8_commande_o_selection_par : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal M9_codeur_i2s_o_dat : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal calcul_param_1_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_2_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_3_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal clk_1 : STD_LOGIC;
+  signal decodeur_i2s_o_dat_right : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal decodeur_i2s_o_str_dat : STD_LOGIC;
+  signal i_btn_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal i_dat_left_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_dat_right_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal i_sw_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal module_commande_0_o_selection_fct : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal mux4_1_output : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal sig_fct_3_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_1_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_100MHz : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_100MHZ CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_100MHz : signal is "XIL_INTERFACENAME CLK.CLK_100MHZ, CLK_DOMAIN design_1_clk_100MHz, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
+begin
+  JPmod(7 downto 0) <= M10_conversion_affichage_JPmod(7 downto 0);
+  clk_1 <= clk_100MHz;
+  i_btn_1(3 downto 0) <= i_btn(3 downto 0);
+  i_data_1 <= i_recdat;
+  i_lrc_1 <= i_lrc;
+  i_sw_1(3 downto 0) <= i_sw(3 downto 0);
+  o_param(7 downto 0) <= mux4_1_output(7 downto 0);
+  o_pbdat(0) <= M9_codeur_i2s_o_dat(0);
+  o_sel_fct(1 downto 0) <= module_commande_0_o_selection_fct(1 downto 0);
+  o_sel_par(1 downto 0) <= M8_commande_o_selection_par(1 downto 0);
+M10_conversion_affichage: component design_1_affhexPmodSSD_v3_0_0
+     port map (
+      DA(7 downto 0) => mux4_1_output(7 downto 0),
+      JPmod(7 downto 0) => M10_conversion_affichage_JPmod(7 downto 0),
+      clk => clk_1,
+      i_btn(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      reset => i_reset_1
+    );
+M1_decodeur_i2s: entity work.M1_decodeur_i2s_imp_17RYJKZ
+     port map (
+      clk => clk_1,
+      i_data => i_data_1,
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      o_dat_right(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_str_dat => decodeur_i2s_o_str_dat
+    );
+M2_fonction_distortion_dure1: component design_1_sig_fct_sat_dure_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0)
+    );
+M3_fonction_distorsion_dure2: component design_1_sig_fct_sat_dure_0_1
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0)
+    );
+M4_fonction3: component design_1_sig_fct_3_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0)
+    );
+M5_parametre_1: component design_1_calcul_param_1_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_1_0_o_param(7 downto 0)
+    );
+M6_parametre_2: component design_1_calcul_param_2_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_2_0_o_param(7 downto 0)
+    );
+M7_parametre_3: component design_1_calcul_param_3_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_3_0_o_param(7 downto 0)
+    );
+M8_commande: component design_1_module_commande_0_0
+     port map (
+      clk => clk_1,
+      i_btn(3 downto 0) => i_btn_1(3 downto 0),
+      i_sw(3 downto 0) => i_sw_1(3 downto 0),
+      o_btn_cd(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      o_reset => i_reset_1,
+      o_selection_fct(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0),
+      o_selection_par(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+M9_codeur_i2s: entity work.M9_codeur_i2s_imp_1VJCTGL
+     port map (
+      i_bclk => clk_1,
+      i_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      i_dat_right(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat(0) => M9_codeur_i2s_o_dat(0)
+    );
+Multiplexeur_choix_fonction: component design_1_mux4_0_0
+     port map (
+      input0(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      input1(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0),
+      input2(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0),
+      input3(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0),
+      output0(23 downto 0) => i_dat_right_1(23 downto 0),
+      sel(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0)
+    );
+Multiplexeur_choix_parametre: component design_1_mux4_0_1
+     port map (
+      input0(7 downto 0) => xlconstant_0_dout(7 downto 0),
+      input1(7 downto 0) => calcul_param_1_0_o_param(7 downto 0),
+      input2(7 downto 0) => calcul_param_2_0_o_param(7 downto 0),
+      input3(7 downto 0) => calcul_param_3_0_o_param(7 downto 0),
+      output0(7 downto 0) => mux4_1_output(7 downto 0),
+      sel(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+parametre_0: component design_1_xlconstant_0_0
+     port map (
+      dout(7 downto 0) => xlconstant_0_dout(7 downto 0)
+    );
+end STRUCTURE;