Batman

372 files changed, 55067 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..648f86b
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,283 @@
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########################################################################################################
+#########
+#Exclude all
+#########
+*
+!*/
+!.gitignore
+###########################################################################
+##	VIVADO
+###########################################################################
+#########
+#Source files:
+#########
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
+!*.vhd
+!*.v
+!*.sv
+!*.bd
+!*.edif
+#########
+#IP files
+#########
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
+#.xci + .dcp: implementation possible but not re-synthesis
+#*.xci(www.spiritconsortium.org)
+!*.xci
+#.xcix: Core container file
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
+!*.xcix
+#*.dcp(checkpoint files)
+!*.dcp
+!*.vds
+!*.pb
+#All bd comments and layout coordinates are stored within .ui
+!*.ui
+!*.ooc
+#########
+#System Generator
+#########
+!*.mdl
+!*.slx
+!*.bxml
+#########
+#Simulation logic analyzer
+#########
+!*.wcfg
+!*.coe
+#########
+#MIG
+#########
+!*.prj
+!*.mem
+#########
+#Project files
+#########
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+pb_APP_log_comb.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#########
+#Constraint files
+#########
+#Do NOT ignore *.xdc files
+!*.xdc
+#########
+#TCL - files
+#########
+!*.tcl
+#########
+#Journal - files
+#########
+!*.jou
+#########
+#Reports
+#########
+!*.rpt
+!*.txt
+!*.vdi
+#########
+#C-files
+#########
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########################################################################################################
+#########
+#Exclude all
+#########
+*
+!*/
+!.gitignore
+###########################################################################
+##	VIVADO
+###########################################################################
+#########
+#Source files:
+#########
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
+!*.vhd
+!*.v
+!*.sv
+!*.bd
+!*.edif
+#########
+#IP files
+#########
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
+#.xci + .dcp: implementation possible but not re-synthesis
+#*.xci(www.spiritconsortium.org)
+!*.xci
+#.xcix: Core container file
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
+!*.xcix
+#*.dcp(checkpoint files)
+!*.dcp
+!*.vds
+!*.pb
+#All bd comments and layout coordinates are stored within .ui
+!*.ui
+!*.ooc
+#########
+#System Generator
+#########
+!*.mdl
+!*.slx
+!*.bxml
+#########
+#Simulation logic analyzer
+#########
+!*.wcfg
+!*.coe
+#########
+#MIG
+#########
+!*.prj
+!*.mem
+#########
+#Project files
+#########
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#########
+#Constraint files
+#########
+#Do NOT ignore *.xdc files
+!*.xdc
+#########
+#TCL - files
+#########
+!*.tcl
+#########
+#Journal - files
+#########
+!*.jou
+#########
+#Reports
+#########
+!*.rpt
+!*.txt
+!*.vdi
+#########
+#C-files
+#########
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########################################################################################################
+#########
+#Exclude all
+#########
+*
+!*/
+!.gitignore
+###########################################################################
+##	VIVADO
+###########################################################################
+#########
+#Source files:
+#########
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
+!*.vhd
+!*.v
+!*.sv
+!*.bd
+!*.edif
+#########
+#IP files
+#########
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
+#.xci + .dcp: implementation possible but not re-synthesis
+#*.xci(www.spiritconsortium.org)
+!*.xci
+#.xcix: Core container file
+#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
+!*.xcix
+#*.dcp(checkpoint files)
+!*.dcp
+!*.vds
+!*.pb
+#All bd comments and layout coordinates are stored within .ui
+!*.ui
+!*.ooc
+#########
+#System Generator
+#########
+!*.mdl
+!*.slx
+!*.bxml
+#########
+#Simulation logic analyzer
+#########
+!*.wcfg
+!*.coe
+#########
+#MIG
+#########
+!*.prj
+!*.mem
+#########
+#Project files
+#########
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+!*.xml
+#########
+#Constraint files
+#########
+#Do NOT ignore *.xdc files
+!*.xdc
+#########
+#TCL - files
+#########
+!*.tcl
+#########
+#Journal - files
+#########
+!*.jou
+#########
+#Reports
+#########
+!*.rpt
+!*.txt
+!*.vdi
+#########
+#C-files
+#########
+!*.c
+!*.h
+!*.elf
+!*.bmm
+!*.xmp
+#########
+#Caches and runs
+#########
+*.cache/
+*.runs/
+# Documentation
+!Readme.md
+# Report in LaTeX
+!*.sty
+!*.tex
+!*.png
+!*.jpg
+# TEMPORARY: Avoid collab conflicts
+pb_APP_log_comb.xpr
diff --git a/leftInput.txt b/leftInput.txt
new file mode 100644
index 0000000..4c2dab6
--- /dev/null
+++ b/leftInput.txt
@@ -0,0 +1,48 @@
+000000

+0C866D

+18D609

+24B8F4

+2FFB28

+3A6B60

+43DBED

+4C237E

+531DD9

+58AC72

+5CB6F8

+5F2BBC

+5FFFFE

+5F301C

+5CBFA5

+58B946

+532E9C

+4C37E7

+43F3A1

+3A85F9

+301832

+24D7EE

+18F66D

+0CA7AC

+002189

+F39AD4

+E74A5D

+DB660A

+D021E7

+C5AF40

+BC3BD0

+B3F0F4

+ACF2F5

+A7606D

+A351C0

+A0D8B0

+A0000E

+A0CB8F

+A337B9

+A739F1

+ACC0AC

+B3B3BA

+BBF4B2

+C55F75

+CFCACB

+DB091C

+E6E933

+F33716
\ No newline at end of file
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml b/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml
new file mode 100644
index 0000000..6303a3a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/design_1.bxml
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+  <CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1747242954"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1747242954"/>
+    <Generation Name="SIMULATION" State="STALE" Timestamp="1747242954"/>
+    <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1747242954"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="synth/design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+      </File>
+      <File Name="sim/design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="design_1_ooc.xdc" Type="XDC">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="OUT_OF_CONTEXT"/>
+      </File>
+      <File Name="hw_handoff/design_1.hwh" Type="HwHandoff">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="design_1.bda">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="hw_handoff/design_1_bd.tcl">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="synth/design_1.hwdef">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="sim/design_1.protoinst">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+    </FileCollection>
+  </CompositeFile>
+</Root>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/design_1_ooc.xdc b/pb_logique_seq.gen/sources_1/bd/design_1/design_1_ooc.xdc
new file mode 100644
index 0000000..64cecb8
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/design_1_ooc.xdc
@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name clk_100MHz -period 10 [get_ports clk_100MHz]
+
+################################################################################
\ No newline at end of file
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
new file mode 100644
index 0000000..792a63b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
@@ -0,0 +1,58 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Jan 16 11:48:36 2024
+--Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+--Command     : generate_target design_1_wrapper.bd
+--Design      : design_1_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1_wrapper is
+  port (
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_recdat : in STD_LOGIC;
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+end design_1_wrapper;
+
+architecture STRUCTURE of design_1_wrapper is
+  component design_1 is
+  port (
+    i_recdat : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1;
+begin
+design_1_i: component design_1
+     port map (
+      JPmod(7 downto 0) => JPmod(7 downto 0),
+      clk_100MHz => clk_100MHz,
+      i_btn(3 downto 0) => i_btn(3 downto 0),
+      i_lrc => i_lrc,
+      i_recdat => i_recdat,
+      i_sw(3 downto 0) => i_sw(3 downto 0),
+      o_param(7 downto 0) => o_param(7 downto 0),
+      o_pbdat(0) => o_pbdat(0),
+      o_sel_fct(1 downto 0) => o_sel_fct(1 downto 0),
+      o_sel_par(1 downto 0) => o_sel_par(1 downto 0)
+    );
+end STRUCTURE;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl b/pb_logique_seq.gen/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
new file mode 100644
index 0000000..296bb2b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
@@ -0,0 +1,630 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+
+# The design that will be created by this Tcl script contains the following 
+# module references:
+# affhexPmodSSD_v3, sig_fct_sat_dure, sig_fct_sat_dure, sig_fct_3, calcul_param_1, calcul_param_2, calcul_param_3, module_commande, mux4, mux4, mef_decod_i2s_v1b, compteur_nbits, reg_24b, reg_24b, reg_dec_24b, compteur_nbits, mef_cod_i2s_vsb, mux2, reg_dec_24b_fd
+
+# Please add the sources of those modules before sourcing this Tcl script.
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z010clg400-1
+   set_property BOARD_PART digilentinc.com:zybo-z7-10:part0:1.0 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+  # Add USER_COMMENTS on $design_name
+  set_property USER_COMMENTS.comment_1 "Modules à modifier:
+MEF_decodeur_i2s (dans M1_decodeur_i2s)
+M5_parametre_1
+M6_parametre_2
+M8_commande
+Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+" [get_bd_designs $design_name]
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: M9_codeur_i2s
+proc create_hier_cell_M9_codeur_i2s { parentCell nameHier } {
+
+  variable script_folder
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_M9_codeur_i2s() - Empty argument(s)!"}
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  # Create interface pins
+
+  # Create pins
+  create_bd_pin -dir I i_bclk
+  create_bd_pin -dir I -from 23 -to 0 i_dat_left
+  create_bd_pin -dir I -from 23 -to 0 i_dat_right
+  create_bd_pin -dir I i_lrc
+  create_bd_pin -dir I -type rst i_reset
+  create_bd_pin -dir O -from 0 -to 0 o_dat
+
+  # Create instance: compteur_nbits_0, and set properties
+  set block_name compteur_nbits
+  set block_cell_name compteur_nbits_0
+  if { [catch {set compteur_nbits_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $compteur_nbits_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.nbits {7} \
+ ] $compteur_nbits_0
+
+  # Create instance: mef_cod_i2s_vsb_0, and set properties
+  set block_name mef_cod_i2s_vsb
+  set block_cell_name mef_cod_i2s_vsb_0
+  if { [catch {set mef_cod_i2s_vsb_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $mef_cod_i2s_vsb_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: mux2_0, and set properties
+  set block_name mux2
+  set block_cell_name mux2_0
+  if { [catch {set mux2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $mux2_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: reg_dec_24b_fd_0, and set properties
+  set block_name reg_dec_24b_fd
+  set block_cell_name reg_dec_24b_fd_0
+  if { [catch {set reg_dec_24b_fd_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $reg_dec_24b_fd_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: xlconcat_0, and set properties
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+
+  # Create instance: xlslice_0, and set properties
+  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {23} \
+   CONFIG.DIN_TO {23} \
+   CONFIG.DIN_WIDTH {24} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_0
+
+  # Create port connections
+  connect_bd_net -net compteur_nbits_0_o_val_cpt [get_bd_pins compteur_nbits_0/o_val_cpt] [get_bd_pins mef_cod_i2s_vsb_0/i_cpt_bits]
+  connect_bd_net -net i_bclk_0_1 [get_bd_pins i_bclk] [get_bd_pins compteur_nbits_0/clk] [get_bd_pins mef_cod_i2s_vsb_0/i_bclk] [get_bd_pins reg_dec_24b_fd_0/i_clk]
+  connect_bd_net -net i_lrc_0_1 [get_bd_pins i_lrc] [get_bd_pins mef_cod_i2s_vsb_0/i_lrc]
+  connect_bd_net -net i_reset_0_1 [get_bd_pins i_reset] [get_bd_pins mef_cod_i2s_vsb_0/i_reset] [get_bd_pins reg_dec_24b_fd_0/i_reset]
+  connect_bd_net -net input1_0_1 [get_bd_pins i_dat_left] [get_bd_pins mux2_0/input1]
+  connect_bd_net -net input2_0_1 [get_bd_pins i_dat_right] [get_bd_pins mux2_0/input2]
+  connect_bd_net -net mef_cod_i2s_vsb_0_o_bit_enable [get_bd_pins compteur_nbits_0/i_en] [get_bd_pins mef_cod_i2s_vsb_0/o_bit_enable] [get_bd_pins reg_dec_24b_fd_0/i_en]
+  connect_bd_net -net mef_cod_i2s_vsb_0_o_cpt_bit_reset [get_bd_pins compteur_nbits_0/reset] [get_bd_pins mef_cod_i2s_vsb_0/o_cpt_bit_reset]
+  connect_bd_net -net mef_cod_i2s_vsb_0_o_load_left [get_bd_pins mef_cod_i2s_vsb_0/o_load_left] [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins xlconcat_0/In0]
+  connect_bd_net -net mef_cod_i2s_vsb_0_o_load_right [get_bd_pins mef_cod_i2s_vsb_0/o_load_right] [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net mux2_0_output [get_bd_pins mux2_0/output0] [get_bd_pins reg_dec_24b_fd_0/i_dat_load]
+  connect_bd_net -net reg_dec_24b_fd_0_o_dat [get_bd_pins reg_dec_24b_fd_0/o_dat] [get_bd_pins xlslice_0/Din]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins reg_dec_24b_fd_0/i_load] [get_bd_pins util_vector_logic_0/Res]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins mux2_0/sel] [get_bd_pins xlconcat_0/dout]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins reg_dec_24b_fd_0/i_dat_bit] [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net xlslice_0_Dout [get_bd_pins o_dat] [get_bd_pins xlslice_0/Dout]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+# Hierarchical cell: M1_decodeur_i2s
+proc create_hier_cell_M1_decodeur_i2s { parentCell nameHier } {
+
+  variable script_folder
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_M1_decodeur_i2s() - Empty argument(s)!"}
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  # Create interface pins
+
+  # Create pins
+  create_bd_pin -dir I clk
+  create_bd_pin -dir I i_data
+  create_bd_pin -dir I i_lrc
+  create_bd_pin -dir I i_reset
+  create_bd_pin -dir O -from 23 -to 0 o_dat_left
+  create_bd_pin -dir O -from 23 -to 0 o_dat_right
+  create_bd_pin -dir O o_str_dat
+
+  # Create instance: MEF_decodeur_i2s, and set properties
+  set block_name mef_decod_i2s_v1b
+  set block_cell_name MEF_decodeur_i2s
+  if { [catch {set MEF_decodeur_i2s [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $MEF_decodeur_i2s eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: compteur_7bits, and set properties
+  set block_name compteur_nbits
+  set block_cell_name compteur_7bits
+  if { [catch {set compteur_7bits [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $compteur_7bits eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.nbits {7} \
+ ] $compteur_7bits
+
+  # Create instance: registre_24bits_droite, and set properties
+  set block_name reg_24b
+  set block_cell_name registre_24bits_droite
+  if { [catch {set registre_24bits_droite [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $registre_24bits_droite eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: registre_24bits_gauche, and set properties
+  set block_name reg_24b
+  set block_cell_name registre_24bits_gauche
+  if { [catch {set registre_24bits_gauche [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $registre_24bits_gauche eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: registre_decalage_24bits, and set properties
+  set block_name reg_dec_24b
+  set block_cell_name registre_decalage_24bits
+  if { [catch {set registre_decalage_24bits [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $registre_decalage_24bits eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+
+  # Create instance: xlconstant_1, and set properties
+  set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+  set_property -dict [ list \
+   CONFIG.CONST_WIDTH {24} \
+ ] $xlconstant_1
+
+  # Create port connections
+  connect_bd_net -net clk_1 [get_bd_pins clk] [get_bd_pins MEF_decodeur_i2s/i_bclk] [get_bd_pins compteur_7bits/clk] [get_bd_pins registre_24bits_droite/i_clk] [get_bd_pins registre_24bits_gauche/i_clk] [get_bd_pins registre_decalage_24bits/i_clk]
+  connect_bd_net -net compteur_nbits_0_o_val_cpt [get_bd_pins MEF_decodeur_i2s/i_cpt_bits] [get_bd_pins compteur_7bits/o_val_cpt]
+  connect_bd_net -net i_data_1 [get_bd_pins i_data] [get_bd_pins registre_decalage_24bits/i_dat_bit]
+  connect_bd_net -net i_lrc_1 [get_bd_pins i_lrc] [get_bd_pins MEF_decodeur_i2s/i_lrc]
+  connect_bd_net -net i_reset_1 [get_bd_pins i_reset] [get_bd_pins MEF_decodeur_i2s/i_reset] [get_bd_pins registre_24bits_droite/i_reset] [get_bd_pins registre_24bits_gauche/i_reset] [get_bd_pins registre_decalage_24bits/i_reset]
+  connect_bd_net -net mef_decod_i2s_v1b_0_o_bit_enable [get_bd_pins MEF_decodeur_i2s/o_bit_enable] [get_bd_pins compteur_7bits/i_en] [get_bd_pins registre_decalage_24bits/i_en]
+  connect_bd_net -net mef_decod_i2s_v1b_0_o_cpt_bit_reset [get_bd_pins MEF_decodeur_i2s/o_cpt_bit_reset] [get_bd_pins compteur_7bits/reset]
+  connect_bd_net -net mef_decod_i2s_v1b_0_o_load_left [get_bd_pins MEF_decodeur_i2s/o_load_left] [get_bd_pins registre_24bits_gauche/i_en]
+  connect_bd_net -net mef_decod_i2s_v1b_0_o_load_right [get_bd_pins MEF_decodeur_i2s/o_load_right] [get_bd_pins registre_24bits_droite/i_en]
+  connect_bd_net -net mef_decod_i2s_v1b_0_o_str_dat [get_bd_pins o_str_dat] [get_bd_pins MEF_decodeur_i2s/o_str_dat]
+  connect_bd_net -net reg_24b_0_o_dat [get_bd_pins o_dat_right] [get_bd_pins registre_24bits_droite/o_dat]
+  connect_bd_net -net reg_24b_1_o_dat [get_bd_pins o_dat_left] [get_bd_pins registre_24bits_gauche/o_dat]
+  connect_bd_net -net reg_dec_24b_0_o_dat [get_bd_pins registre_24bits_droite/i_dat] [get_bd_pins registre_24bits_gauche/i_dat] [get_bd_pins registre_decalage_24bits/o_dat]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins registre_decalage_24bits/i_load] [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net xlconstant_1_dout [get_bd_pins registre_decalage_24bits/i_dat_load] [get_bd_pins xlconstant_1/dout]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+  set JPmod [ create_bd_port -dir O -from 7 -to 0 JPmod ]
+  set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ]
+  set i_btn [ create_bd_port -dir I -from 3 -to 0 i_btn ]
+  set i_lrc [ create_bd_port -dir I i_lrc ]
+  set i_recdat [ create_bd_port -dir I i_recdat ]
+  set i_sw [ create_bd_port -dir I -from 3 -to 0 i_sw ]
+  set o_param [ create_bd_port -dir O -from 7 -to 0 o_param ]
+  set o_pbdat [ create_bd_port -dir O -from 0 -to 0 o_pbdat ]
+  set o_sel_fct [ create_bd_port -dir O -from 1 -to 0 o_sel_fct ]
+  set o_sel_par [ create_bd_port -dir O -from 1 -to 0 o_sel_par ]
+
+  # Create instance: M10_conversion_affichage, and set properties
+  set block_name affhexPmodSSD_v3
+  set block_cell_name M10_conversion_affichage
+  if { [catch {set M10_conversion_affichage [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M10_conversion_affichage eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M1_decodeur_i2s
+  create_hier_cell_M1_decodeur_i2s [current_bd_instance .] M1_decodeur_i2s
+
+  # Create instance: M2_fonction_distortion_dure1, and set properties
+  set block_name sig_fct_sat_dure
+  set block_cell_name M2_fonction_distortion_dure1
+  if { [catch {set M2_fonction_distortion_dure1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M2_fonction_distortion_dure1 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.c_ech_u24_max {0x7FFFFF} \
+ ] $M2_fonction_distortion_dure1
+
+  # Create instance: M3_fonction_distorsion_dure2, and set properties
+  set block_name sig_fct_sat_dure
+  set block_cell_name M3_fonction_distorsion_dure2
+  if { [catch {set M3_fonction_distorsion_dure2 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M3_fonction_distorsion_dure2 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M4_fonction3, and set properties
+  set block_name sig_fct_3
+  set block_cell_name M4_fonction3
+  if { [catch {set M4_fonction3 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M4_fonction3 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M5_parametre_1, and set properties
+  set block_name calcul_param_1
+  set block_cell_name M5_parametre_1
+  if { [catch {set M5_parametre_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M5_parametre_1 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M6_parametre_2, and set properties
+  set block_name calcul_param_2
+  set block_cell_name M6_parametre_2
+  if { [catch {set M6_parametre_2 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M6_parametre_2 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M7_parametre_3, and set properties
+  set block_name calcul_param_3
+  set block_cell_name M7_parametre_3
+  if { [catch {set M7_parametre_3 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M7_parametre_3 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M8_commande, and set properties
+  set block_name module_commande
+  set block_cell_name M8_commande
+  if { [catch {set M8_commande [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $M8_commande eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: M9_codeur_i2s
+  create_hier_cell_M9_codeur_i2s [current_bd_instance .] M9_codeur_i2s
+
+  # Create instance: Multiplexeur_choix_fonction, and set properties
+  set block_name mux4
+  set block_cell_name Multiplexeur_choix_fonction
+  if { [catch {set Multiplexeur_choix_fonction [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $Multiplexeur_choix_fonction eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: Multiplexeur_choix_parametre, and set properties
+  set block_name mux4
+  set block_cell_name Multiplexeur_choix_parametre
+  if { [catch {set Multiplexeur_choix_parametre [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $Multiplexeur_choix_parametre eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.input_length {8} \
+ ] $Multiplexeur_choix_parametre
+
+  # Create instance: parametre_0, and set properties
+  set parametre_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 parametre_0 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+   CONFIG.CONST_WIDTH {8} \
+ ] $parametre_0
+
+  # Create port connections
+  connect_bd_net -net M10_conversion_affichage_JPmod [get_bd_ports JPmod] [get_bd_pins M10_conversion_affichage/JPmod]
+  connect_bd_net -net M8_commande_o_btn_cd [get_bd_pins M10_conversion_affichage/i_btn] [get_bd_pins M8_commande/o_btn_cd]
+  connect_bd_net -net M8_commande_o_selection_par [get_bd_ports o_sel_par] [get_bd_pins M8_commande/o_selection_par] [get_bd_pins Multiplexeur_choix_parametre/sel]
+  connect_bd_net -net M9_codeur_i2s_o_dat [get_bd_ports o_pbdat] [get_bd_pins M9_codeur_i2s/o_dat]
+  connect_bd_net -net calcul_param_1_0_o_param [get_bd_pins M5_parametre_1/o_param] [get_bd_pins Multiplexeur_choix_parametre/input1]
+  connect_bd_net -net calcul_param_2_0_o_param [get_bd_pins M6_parametre_2/o_param] [get_bd_pins Multiplexeur_choix_parametre/input2]
+  connect_bd_net -net calcul_param_3_0_o_param [get_bd_pins M7_parametre_3/o_param] [get_bd_pins Multiplexeur_choix_parametre/input3]
+  connect_bd_net -net clk_1 [get_bd_ports clk_100MHz] [get_bd_pins M10_conversion_affichage/clk] [get_bd_pins M1_decodeur_i2s/clk] [get_bd_pins M5_parametre_1/i_bclk] [get_bd_pins M6_parametre_2/i_bclk] [get_bd_pins M7_parametre_3/i_bclk] [get_bd_pins M8_commande/clk] [get_bd_pins M9_codeur_i2s/i_bclk]
+  connect_bd_net -net decodeur_i2s_o_dat_right [get_bd_pins M1_decodeur_i2s/o_dat_right] [get_bd_pins M2_fonction_distortion_dure1/i_ech] [get_bd_pins M3_fonction_distorsion_dure2/i_ech] [get_bd_pins M4_fonction3/i_ech] [get_bd_pins Multiplexeur_choix_fonction/input0]
+  connect_bd_net -net decodeur_i2s_o_str_dat [get_bd_pins M1_decodeur_i2s/o_str_dat] [get_bd_pins M5_parametre_1/i_en] [get_bd_pins M6_parametre_2/i_en] [get_bd_pins M7_parametre_3/i_en]
+  connect_bd_net -net i_btn_1 [get_bd_ports i_btn] [get_bd_pins M8_commande/i_btn]
+  connect_bd_net -net i_dat_left_1 [get_bd_pins M1_decodeur_i2s/o_dat_left] [get_bd_pins M9_codeur_i2s/i_dat_left]
+  connect_bd_net -net i_dat_right_1 [get_bd_pins M5_parametre_1/i_ech] [get_bd_pins M6_parametre_2/i_ech] [get_bd_pins M7_parametre_3/i_ech] [get_bd_pins M9_codeur_i2s/i_dat_right] [get_bd_pins Multiplexeur_choix_fonction/output0]
+  connect_bd_net -net i_data_1 [get_bd_ports i_recdat] [get_bd_pins M1_decodeur_i2s/i_data]
+  connect_bd_net -net i_lrc_1 [get_bd_ports i_lrc] [get_bd_pins M1_decodeur_i2s/i_lrc] [get_bd_pins M9_codeur_i2s/i_lrc]
+  connect_bd_net -net i_reset_1 [get_bd_pins M10_conversion_affichage/reset] [get_bd_pins M1_decodeur_i2s/i_reset] [get_bd_pins M5_parametre_1/i_reset] [get_bd_pins M6_parametre_2/i_reset] [get_bd_pins M7_parametre_3/i_reset] [get_bd_pins M8_commande/o_reset] [get_bd_pins M9_codeur_i2s/i_reset]
+  connect_bd_net -net i_sw_1 [get_bd_ports i_sw] [get_bd_pins M8_commande/i_sw]
+  connect_bd_net -net module_commande_0_o_selection_fct [get_bd_ports o_sel_fct] [get_bd_pins M8_commande/o_selection_fct] [get_bd_pins Multiplexeur_choix_fonction/sel]
+  connect_bd_net -net mux4_1_output [get_bd_ports o_param] [get_bd_pins M10_conversion_affichage/DA] [get_bd_pins Multiplexeur_choix_parametre/output0]
+  connect_bd_net -net sig_fct_3_0_o_ech_fct [get_bd_pins M4_fonction3/o_ech_fct] [get_bd_pins Multiplexeur_choix_fonction/input3]
+  connect_bd_net -net sig_fct_sat_dure_0_o_ech_fct [get_bd_pins M2_fonction_distortion_dure1/o_ech_fct] [get_bd_pins Multiplexeur_choix_fonction/input1]
+  connect_bd_net -net sig_fct_sat_dure_1_o_ech_fct [get_bd_pins M3_fonction_distorsion_dure2/o_ech_fct] [get_bd_pins Multiplexeur_choix_fonction/input2]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins Multiplexeur_choix_parametre/input0] [get_bd_pins parametre_0/dout]
+
+  # Create address segments
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xml
new file mode 100644
index 0000000..c915b55
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xml
@@ -0,0 +1,235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M10_conversion_affichage_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>DA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>JPmod</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>const_CLK_Hz</spirit:name>
+        <spirit:displayName>Const Clk Hz</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:affhexPmodSSD_v3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>const_CLK_Hz</spirit:name>
+      <spirit:displayName>Const Clk Hz</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M10_conversion_affichage_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>affhexPmodSSD_v3_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml
new file mode 100644
index 0000000..d92a60e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M2_fonction_distortion_dure1_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="unsigned(23 downto 0)">
+        <spirit:name>c_ech_u24_max</spirit:name>
+        <spirit:displayName>C Ech U24 Max</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x7FFFFF</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:sig_fct_sat_dure:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>c_ech_u24_max</spirit:name>
+      <spirit:displayName>C Ech U24 Max</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x7FFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M2_fonction_distortion_dure1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>sig_fct_sat_dure_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_ech_u24_max" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml
new file mode 100644
index 0000000..b2cce85
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xml
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M3_fonction_distorsion_dure2_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="unsigned(23 downto 0)">
+        <spirit:name>c_ech_u24_max</spirit:name>
+        <spirit:displayName>C Ech U24 Max</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:sig_fct_sat_dure:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>c_ech_u24_max</spirit:name>
+      <spirit:displayName>C Ech U24 Max</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M3_fonction_distorsion_dure2_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>sig_fct_sat_dure_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml
new file mode 100644
index 0000000..13c57fb
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xml
@@ -0,0 +1,60 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M4_fonction3_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:sig_fct_3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M4_fonction3_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>sig_fct_3_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml
new file mode 100644
index 0000000..5ad0698
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xml
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M5_parametre_1_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:calcul_param_1:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M5_parametre_1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_1_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml
new file mode 100644
index 0000000..e894217
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xml
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M6_parametre_2_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:calcul_param_2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M6_parametre_2_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_2_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml
new file mode 100644
index 0000000..f6bafd7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xml
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M7_parametre_3_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:calcul_param_3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M7_parametre_3_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_3_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml
new file mode 100644
index 0000000..475f524
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xml
@@ -0,0 +1,282 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_M8_commande_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>o_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_sw</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_btn_cd</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_par</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbtn</spirit:name>
+        <spirit:displayName>Nbtn</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbtn">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>mode_simulation</spirit:name>
+        <spirit:displayName>Mode Simulation</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:module_commande:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbtn</spirit:name>
+      <spirit:displayName>Nbtn</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbtn">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mode_simulation</spirit:name>
+      <spirit:displayName>Mode Simulation</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_M8_commande_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>module_commande_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml
new file mode 100644
index 0000000..8354d27
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xml
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_MEF_decodeur_i2s_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_MEF_decodeur_i2s_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml
new file mode 100644
index 0000000..8575b0b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xml
@@ -0,0 +1,136 @@
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+  <spirit:library>customized_ip</spirit:library>
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+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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+  <spirit:description>xilinx.com:module_ref:mux4:1.0</spirit:description>
+  <spirit:parameters>
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+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_Multiplexeur_choix_fonction_0</spirit:value>
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+  <spirit:vendorExtensions>
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+      <xilinx:displayName>mux4_v1_0</xilinx:displayName>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml
new file mode 100644
index 0000000..8da7108
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xml
@@ -0,0 +1,139 @@
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_Multiplexeur_choix_parametre_0</spirit:name>
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+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>input1</spirit:name>
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+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">8</spirit:value>
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+    <spirit:parameter>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_Multiplexeur_choix_parametre_0</spirit:value>
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+      <xilinx:displayName>mux4_v1_0</xilinx:displayName>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml
new file mode 100644
index 0000000..515b225
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xml
@@ -0,0 +1,385 @@
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+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_affhexPmodSSD_v3_0_0</spirit:name>
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+            <spirit:name>reset</spirit:name>
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+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>affhexPmodSSD_v3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a72dafd7</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_affhexPmodSSD_v3_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a72dafd7</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>affhexPmodSSD_v3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:94feae58</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:94feae58</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_affhexPmodSSD_v3_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:94feae58</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:94feae58</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>DA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>JPmod</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>const_CLK_Hz</spirit:name>
+        <spirit:displayName>Const Clk Hz</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_affhexPmodSSD_v3_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_affhexPmodSSD_v3_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_affhexPmodSSD_v3_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_affhexPmodSSD_v3_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_affhexPmodSSD_v3_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_affhexPmodSSD_v3_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_affhexPmodSSD_v3_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:affhexPmodSSD_v3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>const_CLK_Hz</spirit:name>
+      <spirit:displayName>Const Clk Hz</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_affhexPmodSSD_v3_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>affhexPmodSSD_v3_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
new file mode 100644
index 0000000..0c61365
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_affhexPmodSSD_v3_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_affhexPmodSSD_v3_0_0;
+
+ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT affhexPmodSSD_v3 IS
+    GENERIC (
+      const_CLK_Hz : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT affhexPmodSSD_v3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : affhexPmodSSD_v3
+    GENERIC MAP (
+      const_CLK_Hz => 100000000
+    )
+    PORT MAP (
+      clk => clk,
+      reset => reset,
+      DA => DA,
+      i_btn => i_btn,
+      JPmod => JPmod
+    );
+END design_1_affhexPmodSSD_v3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd
new file mode 100644
index 0000000..863e38e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/synth/design_1_affhexPmodSSD_v3_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_affhexPmodSSD_v3_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_affhexPmodSSD_v3_0_0;
+
+ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT affhexPmodSSD_v3 IS
+    GENERIC (
+      const_CLK_Hz : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT affhexPmodSSD_v3;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "affhexPmodSSD_v3,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_affhexPmodSSD_v3_0_0_arch : ARCHITECTURE IS "design_1_affhexPmodSSD_v3_0_0,affhexPmodSSD_v3,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "design_1_affhexPmodSSD_v3_0_0,affhexPmodSSD_v3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=affhexPmodSSD_v3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,const_CLK_Hz=100000000}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : affhexPmodSSD_v3
+    GENERIC MAP (
+      const_CLK_Hz => 100000000
+    )
+    PORT MAP (
+      clk => clk,
+      reset => reset,
+      DA => DA,
+      i_btn => i_btn,
+      JPmod => JPmod
+    );
+END design_1_affhexPmodSSD_v3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp
new file mode 100644
index 0000000..35abe7c
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml
new file mode 100644
index 0000000..aa175bb
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xml
@@ -0,0 +1,291 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_calcul_param_1_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_1</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:51a74f2b</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_1_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:51a74f2b</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_1</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f071fa08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f071fa08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_1_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f071fa08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 17:00:21 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f071fa08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_calcul_param_1_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_calcul_param_1_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_1_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_1_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_1_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_1_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_1_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_1:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_calcul_param_1_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_1_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v
new file mode 100644
index 0000000..02b702d
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v
@@ -0,0 +1,128 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 12:00:21 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_sim_netlist.v
+// Design      : design_1_calcul_param_1_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_calcul_param_1_0_0,calcul_param_1,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "calcul_param_1,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_calcul_param_1_0_0
+   (i_bclk,
+    i_reset,
+    i_en,
+    i_ech,
+    o_param);
+  input i_bclk;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset;
+  input i_en;
+  input [23:0]i_ech;
+  output [7:0]o_param;
+
+  wire \<const0> ;
+  wire \<const1> ;
+
+  assign o_param[7] = \<const0> ;
+  assign o_param[6] = \<const0> ;
+  assign o_param[5] = \<const0> ;
+  assign o_param[4] = \<const0> ;
+  assign o_param[3] = \<const0> ;
+  assign o_param[2] = \<const0> ;
+  assign o_param[1] = \<const0> ;
+  assign o_param[0] = \<const1> ;
+  GND GND
+       (.G(\<const0> ));
+  VCC VCC
+       (.P(\<const1> ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v
new file mode 100644
index 0000000..136308e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 12:00:21 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0_stub.v

+// Design      : design_1_calcul_param_1_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "calcul_param_1,Vivado 2020.2" *)

+module design_1_calcul_param_1_0_0(i_bclk, i_reset, i_en, i_ech, o_param)

+/* synthesis syn_black_box black_box_pad_pin="i_bclk,i_reset,i_en,i_ech[23:0],o_param[7:0]" */;

+  input i_bclk;

+  input i_reset;

+  input i_en;

+  input [23:0]i_ech;

+  output [7:0]o_param;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
new file mode 100644
index 0000000..b90cd0b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_1_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_1_0_0;
+
+ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_1 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_1;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_1
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_1_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd
new file mode 100644
index 0000000..12f30ce
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/synth/design_1_calcul_param_1_0_0.vhd
@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_1_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_1_0_0;
+
+ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_1 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_1;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "calcul_param_1,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_1_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_1_0_0,calcul_param_1,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_1_0_0,calcul_param_1,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_1,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_1
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_1_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp
new file mode 100644
index 0000000..fc20102
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml
new file mode 100644
index 0000000..9c943ae
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xml
@@ -0,0 +1,291 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_calcul_param_2_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:aa79c05c</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_2_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:aa79c05c</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7d5ec9e3</spirit:value>
+          </spirit:parameter>
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+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7d5ec9e3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_2_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7d5ec9e3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 17:00:21 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7d5ec9e3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_calcul_param_2_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_2_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_2_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_2_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_2_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_2_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_calcul_param_2_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_2_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v
new file mode 100644
index 0000000..60d05dd
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v
@@ -0,0 +1,128 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 12:00:21 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_sim_netlist.v
+// Design      : design_1_calcul_param_2_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_calcul_param_2_0_0,calcul_param_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "calcul_param_2,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_calcul_param_2_0_0
+   (i_bclk,
+    i_reset,
+    i_en,
+    i_ech,
+    o_param);
+  input i_bclk;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset;
+  input i_en;
+  input [23:0]i_ech;
+  output [7:0]o_param;
+
+  wire \<const0> ;
+  wire \<const1> ;
+
+  assign o_param[7] = \<const0> ;
+  assign o_param[6] = \<const0> ;
+  assign o_param[5] = \<const0> ;
+  assign o_param[4] = \<const0> ;
+  assign o_param[3] = \<const0> ;
+  assign o_param[2] = \<const0> ;
+  assign o_param[1] = \<const1> ;
+  assign o_param[0] = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  VCC VCC
+       (.P(\<const1> ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v
new file mode 100644
index 0000000..f6f6e3e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 12:00:21 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0_stub.v

+// Design      : design_1_calcul_param_2_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "calcul_param_2,Vivado 2020.2" *)

+module design_1_calcul_param_2_0_0(i_bclk, i_reset, i_en, i_ech, o_param)

+/* synthesis syn_black_box black_box_pad_pin="i_bclk,i_reset,i_en,i_ech[23:0],o_param[7:0]" */;

+  input i_bclk;

+  input i_reset;

+  input i_en;

+  input [23:0]i_ech;

+  output [7:0]o_param;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
new file mode 100644
index 0000000..aeda442
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_2_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_2_0_0;
+
+ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_2 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_2
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_2_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd
new file mode 100644
index 0000000..6a99f75
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/synth/design_1_calcul_param_2_0_0.vhd
@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_2_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_2_0_0;
+
+ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_2 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_2;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "calcul_param_2,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_2_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_2_0_0,calcul_param_2,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_2_0_0,calcul_param_2,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_2,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_2
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_2_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml
new file mode 100644
index 0000000..96be4aa
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xml
@@ -0,0 +1,287 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_calcul_param_3_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fccc4571</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_3_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fccc4571</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>calcul_param_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b094da85</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b094da85</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_calcul_param_3_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b094da85</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b094da85</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_calcul_param_3_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_calcul_param_3_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_3_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_3_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_3_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_3_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_calcul_param_3_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_calcul_param_3_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>calcul_param_3_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
new file mode 100644
index 0000000..bc012a0
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_3_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_3_0_0;
+
+ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_3 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_3
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd
new file mode 100644
index 0000000..93f83b7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/synth/design_1_calcul_param_3_0_0.vhd
@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_3_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_3_0_0;
+
+ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_3 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_3;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "calcul_param_3,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_calcul_param_3_0_0_arch : ARCHITECTURE IS "design_1_calcul_param_3_0_0,calcul_param_3,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "design_1_calcul_param_3_0_0,calcul_param_3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=calcul_param_3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_3
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml
new file mode 100644
index 0000000..2a80f63
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xml
@@ -0,0 +1,216 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_compteur_7bits_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_val_cpt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbits&apos;)) - 1)">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbits</spirit:name>
+        <spirit:displayName>Nbits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbits">7</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:compteur_nbits:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbits</spirit:name>
+      <spirit:displayName>Nbits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbits">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_compteur_7bits_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>compteur_nbits_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml
new file mode 100644
index 0000000..914dae7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xml
@@ -0,0 +1,365 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_compteur_nbits_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f6adf5ff</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_compteur_nbits_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f6adf5ff</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8075707d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8075707d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_compteur_nbits_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8075707d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8075707d</spirit:value>
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+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_val_cpt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbits&apos;)) - 1)">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbits</spirit:name>
+        <spirit:displayName>Nbits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbits">7</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
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+  <spirit:fileSets>
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+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
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+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
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+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:compteur_nbits:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbits</spirit:name>
+      <spirit:displayName>Nbits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbits">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_compteur_nbits_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>compteur_nbits_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
new file mode 100644
index 0000000..c58480b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_0;
+
+ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd
new file mode 100644
index 0000000..234773a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/synth/design_1_compteur_nbits_0_0.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_0;
+
+ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "compteur_nbits,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_compteur_nbits_0_0_arch : ARCHITECTURE IS "design_1_compteur_nbits_0_0,compteur_nbits,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "design_1_compteur_nbits_0_0,compteur_nbits,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=compteur_nbits,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbits=7}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml
new file mode 100644
index 0000000..bba6fde
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xml
@@ -0,0 +1,216 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_compteur_nbits_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_val_cpt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbits&apos;)) - 1)">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbits</spirit:name>
+        <spirit:displayName>Nbits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbits">7</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:compteur_nbits:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbits</spirit:name>
+      <spirit:displayName>Nbits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbits">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_compteur_nbits_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>compteur_nbits_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp
new file mode 100644
index 0000000..b63fb8a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml
new file mode 100644
index 0000000..7d71334
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xml
@@ -0,0 +1,369 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_compteur_nbits_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a0b2ffab</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_compteur_nbits_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a0b2ffab</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cdf2cb27</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cdf2cb27</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_compteur_nbits_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cdf2cb27</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:58:52 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cdf2cb27</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_val_cpt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbits&apos;)) - 1)">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbits</spirit:name>
+        <spirit:displayName>Nbits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbits">7</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_compteur_nbits_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_compteur_nbits_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_1.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_1_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_1_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_1_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_compteur_nbits_0_1_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:compteur_nbits:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbits</spirit:name>
+      <spirit:displayName>Nbits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbits">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_compteur_nbits_0_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>compteur_nbits_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v
new file mode 100644
index 0000000..453bb6f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v
@@ -0,0 +1,250 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 11:58:52 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_sim_netlist.v
+// Design      : design_1_compteur_nbits_0_1
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_compteur_nbits_0_1,compteur_nbits,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "compteur_nbits,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_compteur_nbits_0_1
+   (clk,
+    i_en,
+    reset,
+    o_val_cpt);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0" *) input clk;
+  input i_en;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset;
+  output [6:0]o_val_cpt;
+
+  wire clk;
+  wire i_en;
+  wire [6:0]o_val_cpt;
+  wire reset;
+
+  design_1_compteur_nbits_0_1_compteur_nbits U0
+       (.clk(clk),
+        .i_en(i_en),
+        .out(o_val_cpt),
+        .reset(reset));
+endmodule
+
+(* ORIG_REF_NAME = "compteur_nbits" *) 
+module design_1_compteur_nbits_0_1_compteur_nbits
+   (out,
+    i_en,
+    clk,
+    reset);
+  output [6:0]out;
+  input i_en;
+  input clk;
+  input reset;
+
+  wire clk;
+  wire \d_val_cpt[6]_i_2_n_0 ;
+  wire i_en;
+  wire [6:0]out;
+  wire [6:0]plusOp;
+  wire reset;
+
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT1 #(
+    .INIT(2'h1)) 
+    \d_val_cpt[0]_i_1 
+       (.I0(out[0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT2 #(
+    .INIT(4'h6)) 
+    \d_val_cpt[1]_i_1 
+       (.I0(out[0]),
+        .I1(out[1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'h78)) 
+    \d_val_cpt[2]_i_1 
+       (.I0(out[0]),
+        .I1(out[1]),
+        .I2(out[2]),
+        .O(plusOp[2]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT4 #(
+    .INIT(16'h7F80)) 
+    \d_val_cpt[3]_i_1 
+       (.I0(out[1]),
+        .I1(out[0]),
+        .I2(out[2]),
+        .I3(out[3]),
+        .O(plusOp[3]));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'h7FFF8000)) 
+    \d_val_cpt[4]_i_1 
+       (.I0(out[2]),
+        .I1(out[0]),
+        .I2(out[1]),
+        .I3(out[3]),
+        .I4(out[4]),
+        .O(plusOp[4]));
+  LUT6 #(
+    .INIT(64'h7FFFFFFF80000000)) 
+    \d_val_cpt[5]_i_1 
+       (.I0(out[3]),
+        .I1(out[1]),
+        .I2(out[0]),
+        .I3(out[2]),
+        .I4(out[4]),
+        .I5(out[5]),
+        .O(plusOp[5]));
+  LUT3 #(
+    .INIT(8'h78)) 
+    \d_val_cpt[6]_i_1 
+       (.I0(\d_val_cpt[6]_i_2_n_0 ),
+        .I1(out[5]),
+        .I2(out[6]),
+        .O(plusOp[6]));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'h80000000)) 
+    \d_val_cpt[6]_i_2 
+       (.I0(out[4]),
+        .I1(out[2]),
+        .I2(out[0]),
+        .I3(out[1]),
+        .I4(out[3]),
+        .O(\d_val_cpt[6]_i_2_n_0 ));
+  FDCE \d_val_cpt_reg[0] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[0]),
+        .Q(out[0]));
+  FDCE \d_val_cpt_reg[1] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[1]),
+        .Q(out[1]));
+  FDCE \d_val_cpt_reg[2] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[2]),
+        .Q(out[2]));
+  FDCE \d_val_cpt_reg[3] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[3]),
+        .Q(out[3]));
+  FDCE \d_val_cpt_reg[4] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[4]),
+        .Q(out[4]));
+  FDCE \d_val_cpt_reg[5] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[5]),
+        .Q(out[5]));
+  FDCE \d_val_cpt_reg[6] 
+       (.C(clk),
+        .CE(i_en),
+        .CLR(reset),
+        .D(plusOp[6]),
+        .Q(out[6]));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v
new file mode 100644
index 0000000..010bb75
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v
@@ -0,0 +1,23 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 11:58:52 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1_stub.v

+// Design      : design_1_compteur_nbits_0_1

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "compteur_nbits,Vivado 2020.2" *)

+module design_1_compteur_nbits_0_1(clk, i_en, reset, o_val_cpt)

+/* synthesis syn_black_box black_box_pad_pin="clk,i_en,reset,o_val_cpt[6:0]" */;

+  input clk;

+  input i_en;

+  input reset;

+  output [6:0]o_val_cpt;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
new file mode 100644
index 0000000..efc345f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_1 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_1;
+
+ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd
new file mode 100644
index 0000000..9965f7a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/synth/design_1_compteur_nbits_0_1.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_1 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_1;
+
+ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "compteur_nbits,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_compteur_nbits_0_1_arch : ARCHITECTURE IS "design_1_compteur_nbits_0_1,compteur_nbits,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "design_1_compteur_nbits_0_1,compteur_nbits,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=compteur_nbits,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbits=7}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml
new file mode 100644
index 0000000..41f23c5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xml
@@ -0,0 +1,359 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mef_cod_i2s_vsb_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>mef_cod_i2s_vsb</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8a0fb88c</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mef_cod_i2s_vsb_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:8a0fb88c</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>mef_cod_i2s_vsb</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:89a9abf5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:89a9abf5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mef_cod_i2s_vsb_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:89a9abf5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:89a9abf5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_lrc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_cpt_bits</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_bit_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_left</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_right</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_cpt_bit_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_mef_cod_i2s_vsb_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_mef_cod_i2s_vsb_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_mef_cod_i2s_vsb_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_cod_i2s_vsb_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_cod_i2s_vsb_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_cod_i2s_vsb_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_cod_i2s_vsb_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mef_cod_i2s_vsb:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mef_cod_i2s_vsb_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mef_cod_i2s_vsb_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
new file mode 100644
index 0000000..9f669ea
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_cod_i2s_vsb_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_cod_i2s_vsb_0_0;
+
+ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_cod_i2s_vsb IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_cod_i2s_vsb;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_cod_i2s_vsb
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_cod_i2s_vsb_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd
new file mode 100644
index 0000000..5cf3090
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/synth/design_1_mef_cod_i2s_vsb_0_0.vhd
@@ -0,0 +1,110 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_cod_i2s_vsb_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_cod_i2s_vsb_0_0;
+
+ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_cod_i2s_vsb IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_cod_i2s_vsb;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "mef_cod_i2s_vsb,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mef_cod_i2s_vsb_0_0_arch : ARCHITECTURE IS "design_1_mef_cod_i2s_vsb_0_0,mef_cod_i2s_vsb,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "design_1_mef_cod_i2s_vsb_0_0,mef_cod_i2s_vsb,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mef_cod_i2s_vsb,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_cod_i2s_vsb
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_cod_i2s_vsb_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml
new file mode 100644
index 0000000..0617352
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xml
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mef_cod_i2s_vsb_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_lrc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_cpt_bits</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_bit_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_left</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_right</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_cpt_bit_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:mef_cod_i2s_vsb:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mef_cod_i2s_vsb_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mef_cod_i2s_vsb_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml
new file mode 100644
index 0000000..286ae5e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xml
@@ -0,0 +1,372 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mef_decod_i2s_v1b_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>mef_decod_i2s_v1b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:75902b07</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mef_decod_i2s_v1b_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:75902b07</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>mef_decod_i2s_v1b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a9bc969e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a9bc969e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mef_decod_i2s_v1b_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a9bc969e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a9bc969e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_lrc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_cpt_bits</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_bit_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_left</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_right</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_str_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_cpt_bit_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_mef_decod_i2s_v1b_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_mef_decod_i2s_v1b_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_mef_decod_i2s_v1b_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_decod_i2s_v1b_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_decod_i2s_v1b_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_decod_i2s_v1b_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mef_decod_i2s_v1b_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mef_decod_i2s_v1b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mef_decod_i2s_v1b_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mef_decod_i2s_v1b_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
new file mode 100644
index 0000000..63454ae
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_decod_i2s_v1b_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_str_dat : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_decod_i2s_v1b_0_0;
+
+ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_decod_i2s_v1b IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_str_dat : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_decod_i2s_v1b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_decod_i2s_v1b
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_str_dat => o_str_dat,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_decod_i2s_v1b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd
new file mode 100644
index 0000000..d6f2bc5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/synth/design_1_mef_decod_i2s_v1b_0_0.vhd
@@ -0,0 +1,113 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_decod_i2s_v1b_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_str_dat : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_decod_i2s_v1b_0_0;
+
+ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_decod_i2s_v1b IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_str_dat : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_decod_i2s_v1b;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "mef_decod_i2s_v1b,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mef_decod_i2s_v1b_0_0_arch : ARCHITECTURE IS "design_1_mef_decod_i2s_v1b_0_0,mef_decod_i2s_v1b,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "design_1_mef_decod_i2s_v1b_0_0,mef_decod_i2s_v1b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mef_decod_i2s_v1b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_decod_i2s_v1b
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_str_dat => o_str_dat,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_decod_i2s_v1b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml
new file mode 100644
index 0000000..d2cc413
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xml
@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_module_commande_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>o_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.O_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.O_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>module_commande</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:798ced9e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_module_commande_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:48:36 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:798ced9e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>module_commande</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fa176fa8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fa176fa8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_module_commande_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fa176fa8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fa176fa8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_sw</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_btn_cd</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_par</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbtn</spirit:name>
+        <spirit:displayName>Nbtn</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbtn">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>mode_simulation</spirit:name>
+        <spirit:displayName>Mode Simulation</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_module_commande_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_module_commande_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_module_commande_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_module_commande_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_module_commande_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_module_commande_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_module_commande_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:module_commande:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbtn</spirit:name>
+      <spirit:displayName>Nbtn</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbtn">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mode_simulation</spirit:name>
+      <spirit:displayName>Mode Simulation</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_module_commande_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>module_commande_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
new file mode 100644
index 0000000..643d8ee
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
@@ -0,0 +1,109 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:module_commande:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_module_commande_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    o_reset : OUT STD_LOGIC;
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_module_commande_0_0;
+
+ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT module_commande IS
+    GENERIC (
+      nbtn : INTEGER;
+      mode_simulation : STD_LOGIC
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      o_reset : OUT STD_LOGIC;
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT module_commande;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : module_commande
+    GENERIC MAP (
+      nbtn => 4,
+      mode_simulation => '0'
+    )
+    PORT MAP (
+      clk => clk,
+      o_reset => o_reset,
+      i_btn => i_btn,
+      i_sw => i_sw,
+      o_btn_cd => o_btn_cd,
+      o_selection_fct => o_selection_fct,
+      o_selection_par => o_selection_par
+    );
+END design_1_module_commande_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd
new file mode 100644
index 0000000..68509bc
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0/synth/design_1_module_commande_0_0.vhd
@@ -0,0 +1,115 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:module_commande:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_module_commande_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    o_reset : OUT STD_LOGIC;
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_module_commande_0_0;
+
+ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT module_commande IS
+    GENERIC (
+      nbtn : INTEGER;
+      mode_simulation : STD_LOGIC
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      o_reset : OUT STD_LOGIC;
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT module_commande;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_commande,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_module_commande_0_0_arch : ARCHITECTURE IS "design_1_module_commande_0_0,module_commande,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "design_1_module_commande_0_0,module_commande,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=module_commande,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,nbtn=4,mode_simulation=0}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : module_commande
+    GENERIC MAP (
+      nbtn => 4,
+      mode_simulation => '0'
+    )
+    PORT MAP (
+      clk => clk,
+      o_reset => o_reset,
+      i_btn => i_btn,
+      i_sw => i_sw,
+      o_btn_cd => o_btn_cd,
+      o_selection_fct => o_selection_fct,
+      o_selection_par => o_selection_par
+    );
+END design_1_module_commande_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp
new file mode 100644
index 0000000..86264d3
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml
new file mode 100644
index 0000000..7833c19
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xml
@@ -0,0 +1,257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mux2_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>mux2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2d84ddc4</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux2_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2d84ddc4</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>mux2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:09e1266e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:09e1266e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux2_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:09e1266e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 17:01:55 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:09e1266e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">24</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_mux2_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_mux2_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_mux2_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux2_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux2_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux2_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux2_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mux2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mux2_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mux2_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v
new file mode 100644
index 0000000..1d2b0f4
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v
@@ -0,0 +1,331 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 12:01:55 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_sim_netlist.v
+// Design      : design_1_mux2_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_mux2_0_0,mux2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "mux2,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_mux2_0_0
+   (sel,
+    input1,
+    input2,
+    output0);
+  input [1:0]sel;
+  input [23:0]input1;
+  input [23:0]input2;
+  output [23:0]output0;
+
+  wire [23:0]input1;
+  wire [23:0]input2;
+  wire [23:0]output0;
+  wire [1:0]sel;
+
+  design_1_mux2_0_0_mux2 U0
+       (.input1(input1),
+        .input2(input2),
+        .output0(output0),
+        .sel(sel));
+endmodule
+
+(* ORIG_REF_NAME = "mux2" *) 
+module design_1_mux2_0_0_mux2
+   (output0,
+    input1,
+    sel,
+    input2);
+  output [23:0]output0;
+  input [23:0]input1;
+  input [1:0]sel;
+  input [23:0]input2;
+
+  wire [23:0]input1;
+  wire [23:0]input2;
+  wire [23:0]output0;
+  wire [1:0]sel;
+
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[0]_INST_0 
+       (.I0(input1[0]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[0]),
+        .O(output0[0]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[10]_INST_0 
+       (.I0(input1[10]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[10]),
+        .O(output0[10]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[11]_INST_0 
+       (.I0(input1[11]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[11]),
+        .O(output0[11]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[12]_INST_0 
+       (.I0(input1[12]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[12]),
+        .O(output0[12]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[13]_INST_0 
+       (.I0(input1[13]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[13]),
+        .O(output0[13]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[14]_INST_0 
+       (.I0(input1[14]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[14]),
+        .O(output0[14]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[15]_INST_0 
+       (.I0(input1[15]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[15]),
+        .O(output0[15]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[16]_INST_0 
+       (.I0(input1[16]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[16]),
+        .O(output0[16]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[17]_INST_0 
+       (.I0(input1[17]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[17]),
+        .O(output0[17]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[18]_INST_0 
+       (.I0(input1[18]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[18]),
+        .O(output0[18]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[19]_INST_0 
+       (.I0(input1[19]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[19]),
+        .O(output0[19]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[1]_INST_0 
+       (.I0(input1[1]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[1]),
+        .O(output0[1]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[20]_INST_0 
+       (.I0(input1[20]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[20]),
+        .O(output0[20]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[21]_INST_0 
+       (.I0(input1[21]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[21]),
+        .O(output0[21]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[22]_INST_0 
+       (.I0(input1[22]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[22]),
+        .O(output0[22]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[23]_INST_0 
+       (.I0(input1[23]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[23]),
+        .O(output0[23]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[2]_INST_0 
+       (.I0(input1[2]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[2]),
+        .O(output0[2]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[3]_INST_0 
+       (.I0(input1[3]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[3]),
+        .O(output0[3]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[4]_INST_0 
+       (.I0(input1[4]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[4]),
+        .O(output0[4]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[5]_INST_0 
+       (.I0(input1[5]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[5]),
+        .O(output0[5]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[6]_INST_0 
+       (.I0(input1[6]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[6]),
+        .O(output0[6]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[7]_INST_0 
+       (.I0(input1[7]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[7]),
+        .O(output0[7]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[8]_INST_0 
+       (.I0(input1[8]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[8]),
+        .O(output0[8]));
+  LUT4 #(
+    .INIT(16'h3808)) 
+    \output0[9]_INST_0 
+       (.I0(input1[9]),
+        .I1(sel[0]),
+        .I2(sel[1]),
+        .I3(input2[9]),
+        .O(output0[9]));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v
new file mode 100644
index 0000000..56c6bce
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v
@@ -0,0 +1,23 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 12:01:55 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0_stub.v

+// Design      : design_1_mux2_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "mux2,Vivado 2020.2" *)

+module design_1_mux2_0_0(sel, input1, input2, output0)

+/* synthesis syn_black_box black_box_pad_pin="sel[1:0],input1[23:0],input2[23:0],output0[23:0]" */;

+  input [1:0]sel;

+  input [23:0]input1;

+  input [23:0]input2;

+  output [23:0]output0;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
new file mode 100644
index 0000000..ffe2904
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
@@ -0,0 +1,92 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux2_0_0 IS
+  PORT (
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux2_0_0;
+
+ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux2 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux2
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      sel => sel,
+      input1 => input1,
+      input2 => input2,
+      output0 => output0
+    );
+END design_1_mux2_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd
new file mode 100644
index 0000000..c248b9c
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0/synth/design_1_mux2_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux2_0_0 IS
+  PORT (
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux2_0_0;
+
+ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux2 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux2;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_mux2_0_0_arch: ARCHITECTURE IS "mux2,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux2_0_0_arch : ARCHITECTURE IS "design_1_mux2_0_0,mux2,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux2_0_0_arch: ARCHITECTURE IS "design_1_mux2_0_0,mux2,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux2,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=24}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux2
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      sel => sel,
+      input1 => input1,
+      input2 => input2,
+      output0 => output0
+    );
+END design_1_mux2_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml
new file mode 100644
index 0000000..cc1c721
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xml
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mux2_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">24</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:mux2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mux2_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mux2_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml
new file mode 100644
index 0000000..959e149
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xml
@@ -0,0 +1,287 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mux4_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:c024d4a4</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux4_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:c024d4a4</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:95f3fa1f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:95f3fa1f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux4_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:95f3fa1f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:95f3fa1f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>input0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">24</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_mux4_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_mux4_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mux4:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mux4_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mux4_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
new file mode 100644
index 0000000..ae6ac28
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_0 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux4_0_0;
+
+ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd
new file mode 100644
index 0000000..f3272f1
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0/synth/design_1_mux4_0_0.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_0 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux4_0_0;
+
+ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_mux4_0_0_arch: ARCHITECTURE IS "mux4,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux4_0_0_arch : ARCHITECTURE IS "design_1_mux4_0_0,mux4,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux4_0_0_arch: ARCHITECTURE IS "design_1_mux4_0_0,mux4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux4,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=24}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml
new file mode 100644
index 0000000..01e4061
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xml
@@ -0,0 +1,290 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_mux4_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:29affc6f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux4_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:29affc6f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:25519e33</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:25519e33</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_mux4_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:25519e33</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:25519e33</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>input0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">8</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_mux4_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_mux4_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_1.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_1_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_1_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_1_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_mux4_0_1_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mux4:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_mux4_0_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>mux4_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.input_length" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
new file mode 100644
index 0000000..d30d1e5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_1 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_mux4_0_1;
+
+ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 8
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd
new file mode 100644
index 0000000..215809e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1/synth/design_1_mux4_0_1.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_1 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_mux4_0_1;
+
+ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_mux4_0_1_arch: ARCHITECTURE IS "mux4,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mux4_0_1_arch : ARCHITECTURE IS "design_1_mux4_0_1,mux4,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_mux4_0_1_arch: ARCHITECTURE IS "design_1_mux4_0_1,mux4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mux4,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_length=8}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 8
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml
new file mode 100644
index 0000000..888b6e5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xml
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_parametre_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>CONST_WIDTH</spirit:name>
+        <spirit:displayName>Const Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CONST_VAL</spirit:name>
+        <spirit:displayName>Const Val</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_parametre_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml
new file mode 100644
index 0000000..353467a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xml
@@ -0,0 +1,369 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_reg_24b_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:63b2073a</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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+        <spirit:modelName>design_1_reg_24b_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
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+        <spirit:displayName>Synthesis</spirit:displayName>
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+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2dafd90a</spirit:value>
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+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
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+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2dafd90a</spirit:value>
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+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_reg_24b_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2dafd90a</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2dafd90a</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_reg_24b_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_reg_24b_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_reg_24b_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_24b_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
new file mode 100644
index 0000000..4ef9d64
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_0;
+
+ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd
new file mode 100644
index 0000000..9e9d60f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/synth/design_1_reg_24b_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_0;
+
+ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "reg_24b,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_24b_0_0_arch : ARCHITECTURE IS "design_1_reg_24b_0_0,reg_24b,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "design_1_reg_24b_0_0,reg_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml
new file mode 100644
index 0000000..a20b432
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xml
@@ -0,0 +1,369 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_reg_24b_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:87279137</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_reg_24b_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:87279137</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b7bc7d08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b7bc7d08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_reg_24b_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b7bc7d08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b7bc7d08</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_reg_24b_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_reg_24b_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_1.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_1_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_1_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_1_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_24b_0_1_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_reg_24b_0_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_24b_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
new file mode 100644
index 0000000..3883a48
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_1 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_1;
+
+ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd
new file mode 100644
index 0000000..978bba8
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/synth/design_1_reg_24b_0_1.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_1 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_1;
+
+ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "reg_24b,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_24b_0_1_arch : ARCHITECTURE IS "design_1_reg_24b_0_1,reg_24b,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "design_1_reg_24b_0_1,reg_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp
new file mode 100644
index 0000000..06da2bb
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml
new file mode 100644
index 0000000..de17a04
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xml
@@ -0,0 +1,399 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_reg_dec_24b_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
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+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
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+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
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+        <spirit:parameter>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
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+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
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+        <spirit:modelName>reg_dec_24b</spirit:modelName>
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+            <spirit:value>9:2d5a01c5</spirit:value>
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+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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+            <spirit:value>9:31fe9609</spirit:value>
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+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
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+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:31fe9609</spirit:value>
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+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
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+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
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+            <spirit:name>outputProductCRC</spirit:name>
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+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
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+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>i_load</spirit:name>
+        <spirit:wire>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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+        </spirit:wire>
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+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_bit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>i_dat_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
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+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
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+        <spirit:fileType>vhdlSource</spirit:fileType>
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+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
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+        <spirit:name>design_1_reg_dec_24b_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+        <spirit:name>design_1_reg_dec_24b_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_reg_dec_24b_0_0</spirit:value>
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+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v
new file mode 100644
index 0000000..e7edd8b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v
@@ -0,0 +1,504 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 11:58:52 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_sim_netlist.v
+// Design      : design_1_reg_dec_24b_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_reg_dec_24b_0_0,reg_dec_24b,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "reg_dec_24b,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_reg_dec_24b_0_0
+   (i_clk,
+    i_reset,
+    i_load,
+    i_en,
+    i_dat_bit,
+    i_dat_load,
+    o_dat);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 i_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0" *) input i_clk;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 i_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_reset;
+  input i_load;
+  input i_en;
+  input i_dat_bit;
+  input [23:0]i_dat_load;
+  output [23:0]o_dat;
+
+  wire i_clk;
+  wire i_dat_bit;
+  wire [23:0]i_dat_load;
+  wire i_en;
+  wire i_load;
+  wire i_reset;
+  wire [23:0]o_dat;
+
+  design_1_reg_dec_24b_0_0_reg_dec_24b U0
+       (.i_clk(i_clk),
+        .i_dat_bit(i_dat_bit),
+        .i_dat_load(i_dat_load),
+        .i_en(i_en),
+        .i_load(i_load),
+        .i_reset(i_reset),
+        .o_dat(o_dat));
+endmodule
+
+(* ORIG_REF_NAME = "reg_dec_24b" *) 
+module design_1_reg_dec_24b_0_0_reg_dec_24b
+   (o_dat,
+    i_clk,
+    i_reset,
+    i_dat_load,
+    i_load,
+    i_dat_bit,
+    i_en);
+  output [23:0]o_dat;
+  input i_clk;
+  input i_reset;
+  input [23:0]i_dat_load;
+  input i_load;
+  input i_dat_bit;
+  input i_en;
+
+  wire i_clk;
+  wire i_dat_bit;
+  wire [23:0]i_dat_load;
+  wire i_en;
+  wire i_load;
+  wire i_reset;
+  wire [23:0]o_dat;
+  wire [23:0]p_1_in;
+  wire \q_shift_reg[23]_i_1_n_0 ;
+
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[0]_i_1 
+       (.I0(i_dat_load[0]),
+        .I1(i_load),
+        .I2(i_dat_bit),
+        .O(p_1_in[0]));
+  (* SOFT_HLUTNM = "soft_lutpair5" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[10]_i_1 
+       (.I0(i_dat_load[10]),
+        .I1(i_load),
+        .I2(o_dat[9]),
+        .O(p_1_in[10]));
+  (* SOFT_HLUTNM = "soft_lutpair5" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[11]_i_1 
+       (.I0(i_dat_load[11]),
+        .I1(i_load),
+        .I2(o_dat[10]),
+        .O(p_1_in[11]));
+  (* SOFT_HLUTNM = "soft_lutpair6" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[12]_i_1 
+       (.I0(i_dat_load[12]),
+        .I1(i_load),
+        .I2(o_dat[11]),
+        .O(p_1_in[12]));
+  (* SOFT_HLUTNM = "soft_lutpair6" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[13]_i_1 
+       (.I0(i_dat_load[13]),
+        .I1(i_load),
+        .I2(o_dat[12]),
+        .O(p_1_in[13]));
+  (* SOFT_HLUTNM = "soft_lutpair7" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[14]_i_1 
+       (.I0(i_dat_load[14]),
+        .I1(i_load),
+        .I2(o_dat[13]),
+        .O(p_1_in[14]));
+  (* SOFT_HLUTNM = "soft_lutpair7" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[15]_i_1 
+       (.I0(i_dat_load[15]),
+        .I1(i_load),
+        .I2(o_dat[14]),
+        .O(p_1_in[15]));
+  (* SOFT_HLUTNM = "soft_lutpair8" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[16]_i_1 
+       (.I0(i_dat_load[16]),
+        .I1(i_load),
+        .I2(o_dat[15]),
+        .O(p_1_in[16]));
+  (* SOFT_HLUTNM = "soft_lutpair8" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[17]_i_1 
+       (.I0(i_dat_load[17]),
+        .I1(i_load),
+        .I2(o_dat[16]),
+        .O(p_1_in[17]));
+  (* SOFT_HLUTNM = "soft_lutpair9" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[18]_i_1 
+       (.I0(i_dat_load[18]),
+        .I1(i_load),
+        .I2(o_dat[17]),
+        .O(p_1_in[18]));
+  (* SOFT_HLUTNM = "soft_lutpair9" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[19]_i_1 
+       (.I0(i_dat_load[19]),
+        .I1(i_load),
+        .I2(o_dat[18]),
+        .O(p_1_in[19]));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[1]_i_1 
+       (.I0(i_dat_load[1]),
+        .I1(i_load),
+        .I2(o_dat[0]),
+        .O(p_1_in[1]));
+  (* SOFT_HLUTNM = "soft_lutpair10" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[20]_i_1 
+       (.I0(i_dat_load[20]),
+        .I1(i_load),
+        .I2(o_dat[19]),
+        .O(p_1_in[20]));
+  (* SOFT_HLUTNM = "soft_lutpair10" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[21]_i_1 
+       (.I0(i_dat_load[21]),
+        .I1(i_load),
+        .I2(o_dat[20]),
+        .O(p_1_in[21]));
+  (* SOFT_HLUTNM = "soft_lutpair11" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[22]_i_1 
+       (.I0(i_dat_load[22]),
+        .I1(i_load),
+        .I2(o_dat[21]),
+        .O(p_1_in[22]));
+  LUT2 #(
+    .INIT(4'hE)) 
+    \q_shift_reg[23]_i_1 
+       (.I0(i_load),
+        .I1(i_en),
+        .O(\q_shift_reg[23]_i_1_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair11" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[23]_i_2 
+       (.I0(i_dat_load[23]),
+        .I1(i_load),
+        .I2(o_dat[22]),
+        .O(p_1_in[23]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[2]_i_1 
+       (.I0(i_dat_load[2]),
+        .I1(i_load),
+        .I2(o_dat[1]),
+        .O(p_1_in[2]));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[3]_i_1 
+       (.I0(i_dat_load[3]),
+        .I1(i_load),
+        .I2(o_dat[2]),
+        .O(p_1_in[3]));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[4]_i_1 
+       (.I0(i_dat_load[4]),
+        .I1(i_load),
+        .I2(o_dat[3]),
+        .O(p_1_in[4]));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[5]_i_1 
+       (.I0(i_dat_load[5]),
+        .I1(i_load),
+        .I2(o_dat[4]),
+        .O(p_1_in[5]));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[6]_i_1 
+       (.I0(i_dat_load[6]),
+        .I1(i_load),
+        .I2(o_dat[5]),
+        .O(p_1_in[6]));
+  (* SOFT_HLUTNM = "soft_lutpair3" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[7]_i_1 
+       (.I0(i_dat_load[7]),
+        .I1(i_load),
+        .I2(o_dat[6]),
+        .O(p_1_in[7]));
+  (* SOFT_HLUTNM = "soft_lutpair4" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[8]_i_1 
+       (.I0(i_dat_load[8]),
+        .I1(i_load),
+        .I2(o_dat[7]),
+        .O(p_1_in[8]));
+  (* SOFT_HLUTNM = "soft_lutpair4" *) 
+  LUT3 #(
+    .INIT(8'hB8)) 
+    \q_shift_reg[9]_i_1 
+       (.I0(i_dat_load[9]),
+        .I1(i_load),
+        .I2(o_dat[8]),
+        .O(p_1_in[9]));
+  FDCE \q_shift_reg_reg[0] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[0]),
+        .Q(o_dat[0]));
+  FDCE \q_shift_reg_reg[10] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[10]),
+        .Q(o_dat[10]));
+  FDCE \q_shift_reg_reg[11] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[11]),
+        .Q(o_dat[11]));
+  FDCE \q_shift_reg_reg[12] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[12]),
+        .Q(o_dat[12]));
+  FDCE \q_shift_reg_reg[13] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[13]),
+        .Q(o_dat[13]));
+  FDCE \q_shift_reg_reg[14] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[14]),
+        .Q(o_dat[14]));
+  FDCE \q_shift_reg_reg[15] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[15]),
+        .Q(o_dat[15]));
+  FDCE \q_shift_reg_reg[16] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[16]),
+        .Q(o_dat[16]));
+  FDCE \q_shift_reg_reg[17] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[17]),
+        .Q(o_dat[17]));
+  FDCE \q_shift_reg_reg[18] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[18]),
+        .Q(o_dat[18]));
+  FDCE \q_shift_reg_reg[19] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[19]),
+        .Q(o_dat[19]));
+  FDCE \q_shift_reg_reg[1] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[1]),
+        .Q(o_dat[1]));
+  FDCE \q_shift_reg_reg[20] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[20]),
+        .Q(o_dat[20]));
+  FDCE \q_shift_reg_reg[21] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[21]),
+        .Q(o_dat[21]));
+  FDCE \q_shift_reg_reg[22] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[22]),
+        .Q(o_dat[22]));
+  FDCE \q_shift_reg_reg[23] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[23]),
+        .Q(o_dat[23]));
+  FDCE \q_shift_reg_reg[2] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[2]),
+        .Q(o_dat[2]));
+  FDCE \q_shift_reg_reg[3] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[3]),
+        .Q(o_dat[3]));
+  FDCE \q_shift_reg_reg[4] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[4]),
+        .Q(o_dat[4]));
+  FDCE \q_shift_reg_reg[5] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[5]),
+        .Q(o_dat[5]));
+  FDCE \q_shift_reg_reg[6] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[6]),
+        .Q(o_dat[6]));
+  FDCE \q_shift_reg_reg[7] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[7]),
+        .Q(o_dat[7]));
+  FDCE \q_shift_reg_reg[8] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[8]),
+        .Q(o_dat[8]));
+  FDCE \q_shift_reg_reg[9] 
+       (.C(i_clk),
+        .CE(\q_shift_reg[23]_i_1_n_0 ),
+        .CLR(i_reset),
+        .D(p_1_in[9]),
+        .Q(o_dat[9]));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v
new file mode 100644
index 0000000..415c9e7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v
@@ -0,0 +1,27 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 11:58:52 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0_stub.v

+// Design      : design_1_reg_dec_24b_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "reg_dec_24b,Vivado 2020.2" *)

+module design_1_reg_dec_24b_0_0(i_clk, i_reset, i_load, i_en, i_dat_bit, 

+  i_dat_load, o_dat)

+/* synthesis syn_black_box black_box_pad_pin="i_clk,i_reset,i_load,i_en,i_dat_bit,i_dat_load[23:0],o_dat[23:0]" */;

+  input i_clk;

+  input i_reset;

+  input i_load;

+  input i_en;

+  input i_dat_bit;

+  input [23:0]i_dat_load;

+  output [23:0]o_dat;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
new file mode 100644
index 0000000..2dbb12a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd
new file mode 100644
index 0000000..b362042
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/synth/design_1_reg_dec_24b_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "reg_dec_24b,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_dec_24b_0_0_arch : ARCHITECTURE IS "design_1_reg_dec_24b_0_0,reg_dec_24b,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "design_1_reg_dec_24b_0_0,reg_dec_24b,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_dec_24b,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml
new file mode 100644
index 0000000..1c4de0a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xml
@@ -0,0 +1,395 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_reg_dec_24b_fd_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>reg_dec_24b_fd</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:d3ccf6b8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_reg_dec_24b_fd_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:d3ccf6b8</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>reg_dec_24b_fd</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:565ff38d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:565ff38d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_reg_dec_24b_fd_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:565ff38d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:565ff38d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_bit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_reg_dec_24b_fd_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_reg_dec_24b_fd_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_fd_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_fd_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_fd_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_fd_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_reg_dec_24b_fd_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_dec_24b_fd:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_reg_dec_24b_fd_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_dec_24b_fd_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
new file mode 100644
index 0000000..c8a9b85
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_fd_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_fd_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b_fd IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b_fd;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b_fd
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_fd_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd
new file mode 100644
index 0000000..0015b2e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/synth/design_1_reg_dec_24b_fd_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_fd_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_fd_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b_fd IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b_fd;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "reg_dec_24b_fd,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_reg_dec_24b_fd_0_0_arch : ARCHITECTURE IS "design_1_reg_dec_24b_fd_0_0,reg_dec_24b_fd,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "design_1_reg_dec_24b_fd_0_0,reg_dec_24b_fd,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_dec_24b_fd,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b_fd
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_fd_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml
new file mode 100644
index 0000000..d2c2759
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xml
@@ -0,0 +1,243 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_reg_dec_24b_fd_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_bit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:reg_dec_24b_fd:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_reg_dec_24b_fd_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_dec_24b_fd_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml
new file mode 100644
index 0000000..6416776
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xml
@@ -0,0 +1,219 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_registre_24bits_droite_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:reg_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_registre_24bits_droite_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_24b_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml
new file mode 100644
index 0000000..73e2276
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xml
@@ -0,0 +1,219 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_registre_24bits_gauche_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:description>xilinx.com:module_ref:reg_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_registre_24bits_gauche_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>reg_24b_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml
new file mode 100644
index 0000000..3ca96da
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xml
@@ -0,0 +1,243 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_registre_decalage_24bits_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:value>
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+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:value>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp
new file mode 100644
index 0000000..353b99c
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml
new file mode 100644
index 0000000..906e901
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xml
@@ -0,0 +1,211 @@
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v
new file mode 100644
index 0000000..dfd7ce6
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v
@@ -0,0 +1,110 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 12:01:55 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_sim_netlist.v
+// Design      : design_1_sig_fct_3_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_sig_fct_3_0_0,sig_fct_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "sig_fct_3,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_sig_fct_3_0_0
+   (i_ech,
+    o_ech_fct);
+  input [23:0]i_ech;
+  output [23:0]o_ech_fct;
+
+  wire [23:0]i_ech;
+
+  assign o_ech_fct[23:0] = i_ech;
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v
new file mode 100644
index 0000000..23d3fb1
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v
@@ -0,0 +1,21 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 12:01:55 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0_stub.v

+// Design      : design_1_sig_fct_3_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "sig_fct_3,Vivado 2020.2" *)

+module design_1_sig_fct_3_0_0(i_ech, o_ech_fct)

+/* synthesis syn_black_box black_box_pad_pin="i_ech[23:0],o_ech_fct[23:0]" */;

+  input [23:0]i_ech;

+  output [23:0]o_ech_fct;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
new file mode 100644
index 0000000..3a84972
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
@@ -0,0 +1,80 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_3_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_3_0_0;
+
+ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_3 IS
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_3
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd
new file mode 100644
index 0000000..6cc4fff
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/synth/design_1_sig_fct_3_0_0.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_3_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_3_0_0;
+
+ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_3 IS
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_3;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "sig_fct_3,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_3_0_0_arch : ARCHITECTURE IS "design_1_sig_fct_3_0_0,sig_fct_3,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "design_1_sig_fct_3_0_0,sig_fct_3,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_3
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_3_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp
new file mode 100644
index 0000000..8363504
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.dcp
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml
new file mode 100644
index 0000000..5147b3b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xml
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_sig_fct_sat_dure_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>sig_fct_sat_dure</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:18f92d4c</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
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+        <spirit:language>vhdl</spirit:language>
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+        <spirit:parameters>
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+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
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+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
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+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
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+        <spirit:parameters>
+          <spirit:parameter>
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+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
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+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
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+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 17:03:16 UTC 2024</spirit:value>
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+            <spirit:name>outputProductCRC</spirit:name>
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+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
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+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="unsigned(23 downto 0)">
+        <spirit:name>c_ech_u24_max</spirit:name>
+        <spirit:displayName>C Ech U24 Max</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x7FFFFF</spirit:value>
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+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:sig_fct_sat_dure:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>c_ech_u24_max</spirit:name>
+      <spirit:displayName>C Ech U24 Max</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x7FFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_sig_fct_sat_dure_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>sig_fct_sat_dure_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_ech_u24_max" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v
new file mode 100644
index 0000000..a6534d1
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v
@@ -0,0 +1,896 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Tue Jan 16 12:03:16 2024
+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_sim_netlist.v
+// Design      : design_1_sig_fct_sat_dure_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "sig_fct_sat_dure,Vivado 2020.2" *) 
+(* NotValidForBitStream *)
+module design_1_sig_fct_sat_dure_0_0
+   (i_ech,
+    o_ech_fct);
+  input [23:0]i_ech;
+  output [23:0]o_ech_fct;
+
+  wire [23:0]i_ech;
+  wire [23:0]o_ech_fct;
+  wire \o_ech_fct[12]_INST_0_i_10_n_0 ;
+  wire \o_ech_fct[12]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[12]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[12]_INST_0_i_1_n_2 ;
+  wire \o_ech_fct[12]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_0 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_1 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_2 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_3 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_4 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_5 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_6 ;
+  wire \o_ech_fct[12]_INST_0_i_6_n_7 ;
+  wire \o_ech_fct[12]_INST_0_i_7_n_0 ;
+  wire \o_ech_fct[12]_INST_0_i_8_n_0 ;
+  wire \o_ech_fct[12]_INST_0_i_9_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_10_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[16]_INST_0_i_1_n_2 ;
+  wire \o_ech_fct[16]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_1 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_2 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_3 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_4 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_5 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_6 ;
+  wire \o_ech_fct[16]_INST_0_i_6_n_7 ;
+  wire \o_ech_fct[16]_INST_0_i_7_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_8_n_0 ;
+  wire \o_ech_fct[16]_INST_0_i_9_n_0 ;
+  wire \o_ech_fct[20]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[20]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[20]_INST_0_i_1_n_2 ;
+  wire \o_ech_fct[20]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[22]_INST_0_i_10_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_11_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_12_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_13_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_14_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_15_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_16_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_17_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_18_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_19_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_20_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_2_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_3_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_4_n_2 ;
+  wire \o_ech_fct[22]_INST_0_i_4_n_3 ;
+  wire \o_ech_fct[22]_INST_0_i_4_n_5 ;
+  wire \o_ech_fct[22]_INST_0_i_4_n_6 ;
+  wire \o_ech_fct[22]_INST_0_i_4_n_7 ;
+  wire \o_ech_fct[22]_INST_0_i_5_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_6_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_7_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_0 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_1 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_2 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_3 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_4 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_5 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_6 ;
+  wire \o_ech_fct[22]_INST_0_i_8_n_7 ;
+  wire \o_ech_fct[22]_INST_0_i_9_n_0 ;
+  wire \o_ech_fct[23]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[23]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[4]_INST_0_i_10_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_11_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_12_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[4]_INST_0_i_1_n_2 ;
+  wire \o_ech_fct[4]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_1 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_2 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_3 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_4 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_5 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_6 ;
+  wire \o_ech_fct[4]_INST_0_i_7_n_7 ;
+  wire \o_ech_fct[4]_INST_0_i_8_n_0 ;
+  wire \o_ech_fct[4]_INST_0_i_9_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_10_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_1_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_1_n_1 ;
+  wire \o_ech_fct[8]_INST_0_i_1_n_2 ;
+  wire \o_ech_fct[8]_INST_0_i_1_n_3 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_1 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_2 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_3 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_4 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_5 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_6 ;
+  wire \o_ech_fct[8]_INST_0_i_6_n_7 ;
+  wire \o_ech_fct[8]_INST_0_i_7_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_8_n_0 ;
+  wire \o_ech_fct[8]_INST_0_i_9_n_0 ;
+  wire [22:0]p_0_in;
+  wire [22:1]plusOp;
+  wire [3:2]\NLW_o_ech_fct[22]_INST_0_i_4_CO_UNCONNECTED ;
+  wire [3:3]\NLW_o_ech_fct[22]_INST_0_i_4_O_UNCONNECTED ;
+  wire [3:1]\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED ;
+  wire [3:2]\NLW_o_ech_fct[23]_INST_0_i_1_O_UNCONNECTED ;
+
+  LUT2 #(
+    .INIT(4'hE)) 
+    \o_ech_fct[0]_INST_0 
+       (.I0(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I1(i_ech[0]),
+        .O(o_ech_fct[0]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[10]_INST_0 
+       (.I0(plusOp[10]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[10]),
+        .O(o_ech_fct[10]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[11]_INST_0 
+       (.I0(plusOp[11]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[11]),
+        .O(o_ech_fct[11]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[12]_INST_0 
+       (.I0(plusOp[12]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[12]),
+        .O(o_ech_fct[12]));
+  CARRY4 \o_ech_fct[12]_INST_0_i_1 
+       (.CI(\o_ech_fct[8]_INST_0_i_1_n_0 ),
+        .CO({\o_ech_fct[12]_INST_0_i_1_n_0 ,\o_ech_fct[12]_INST_0_i_1_n_1 ,\o_ech_fct[12]_INST_0_i_1_n_2 ,\o_ech_fct[12]_INST_0_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O(plusOp[12:9]),
+        .S(p_0_in[12:9]));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[12]_INST_0_i_10 
+       (.I0(i_ech[9]),
+        .O(\o_ech_fct[12]_INST_0_i_10_n_0 ));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[12]_INST_0_i_2 
+       (.I0(\o_ech_fct[12]_INST_0_i_6_n_4 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[12]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[12]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[12]_INST_0_i_3 
+       (.I0(\o_ech_fct[12]_INST_0_i_6_n_5 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[11]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[11]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[12]_INST_0_i_4 
+       (.I0(\o_ech_fct[12]_INST_0_i_6_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[10]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[10]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[12]_INST_0_i_5 
+       (.I0(\o_ech_fct[12]_INST_0_i_6_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[9]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[9]));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[12]_INST_0_i_6 
+       (.CI(\o_ech_fct[8]_INST_0_i_6_n_0 ),
+        .CO({\o_ech_fct[12]_INST_0_i_6_n_0 ,\o_ech_fct[12]_INST_0_i_6_n_1 ,\o_ech_fct[12]_INST_0_i_6_n_2 ,\o_ech_fct[12]_INST_0_i_6_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\o_ech_fct[12]_INST_0_i_6_n_4 ,\o_ech_fct[12]_INST_0_i_6_n_5 ,\o_ech_fct[12]_INST_0_i_6_n_6 ,\o_ech_fct[12]_INST_0_i_6_n_7 }),
+        .S({\o_ech_fct[12]_INST_0_i_7_n_0 ,\o_ech_fct[12]_INST_0_i_8_n_0 ,\o_ech_fct[12]_INST_0_i_9_n_0 ,\o_ech_fct[12]_INST_0_i_10_n_0 }));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[12]_INST_0_i_7 
+       (.I0(i_ech[12]),
+        .O(\o_ech_fct[12]_INST_0_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[12]_INST_0_i_8 
+       (.I0(i_ech[11]),
+        .O(\o_ech_fct[12]_INST_0_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[12]_INST_0_i_9 
+       (.I0(i_ech[10]),
+        .O(\o_ech_fct[12]_INST_0_i_9_n_0 ));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[13]_INST_0 
+       (.I0(plusOp[13]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[13]),
+        .O(o_ech_fct[13]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[14]_INST_0 
+       (.I0(plusOp[14]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[14]),
+        .O(o_ech_fct[14]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[15]_INST_0 
+       (.I0(plusOp[15]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[15]),
+        .O(o_ech_fct[15]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[16]_INST_0 
+       (.I0(plusOp[16]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[16]),
+        .O(o_ech_fct[16]));
+  CARRY4 \o_ech_fct[16]_INST_0_i_1 
+       (.CI(\o_ech_fct[12]_INST_0_i_1_n_0 ),
+        .CO({\o_ech_fct[16]_INST_0_i_1_n_0 ,\o_ech_fct[16]_INST_0_i_1_n_1 ,\o_ech_fct[16]_INST_0_i_1_n_2 ,\o_ech_fct[16]_INST_0_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O(plusOp[16:13]),
+        .S(p_0_in[16:13]));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[16]_INST_0_i_10 
+       (.I0(i_ech[13]),
+        .O(\o_ech_fct[16]_INST_0_i_10_n_0 ));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[16]_INST_0_i_2 
+       (.I0(\o_ech_fct[16]_INST_0_i_6_n_4 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[16]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[16]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[16]_INST_0_i_3 
+       (.I0(\o_ech_fct[16]_INST_0_i_6_n_5 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[15]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[15]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[16]_INST_0_i_4 
+       (.I0(\o_ech_fct[16]_INST_0_i_6_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[14]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[14]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[16]_INST_0_i_5 
+       (.I0(\o_ech_fct[16]_INST_0_i_6_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[13]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[13]));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[16]_INST_0_i_6 
+       (.CI(\o_ech_fct[12]_INST_0_i_6_n_0 ),
+        .CO({\o_ech_fct[16]_INST_0_i_6_n_0 ,\o_ech_fct[16]_INST_0_i_6_n_1 ,\o_ech_fct[16]_INST_0_i_6_n_2 ,\o_ech_fct[16]_INST_0_i_6_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\o_ech_fct[16]_INST_0_i_6_n_4 ,\o_ech_fct[16]_INST_0_i_6_n_5 ,\o_ech_fct[16]_INST_0_i_6_n_6 ,\o_ech_fct[16]_INST_0_i_6_n_7 }),
+        .S({\o_ech_fct[16]_INST_0_i_7_n_0 ,\o_ech_fct[16]_INST_0_i_8_n_0 ,\o_ech_fct[16]_INST_0_i_9_n_0 ,\o_ech_fct[16]_INST_0_i_10_n_0 }));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[16]_INST_0_i_7 
+       (.I0(i_ech[16]),
+        .O(\o_ech_fct[16]_INST_0_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[16]_INST_0_i_8 
+       (.I0(i_ech[15]),
+        .O(\o_ech_fct[16]_INST_0_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[16]_INST_0_i_9 
+       (.I0(i_ech[14]),
+        .O(\o_ech_fct[16]_INST_0_i_9_n_0 ));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[17]_INST_0 
+       (.I0(plusOp[17]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[17]),
+        .O(o_ech_fct[17]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[18]_INST_0 
+       (.I0(plusOp[18]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[18]),
+        .O(o_ech_fct[18]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[19]_INST_0 
+       (.I0(plusOp[19]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[19]),
+        .O(o_ech_fct[19]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[1]_INST_0 
+       (.I0(plusOp[1]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[1]),
+        .O(o_ech_fct[1]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[20]_INST_0 
+       (.I0(plusOp[20]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[20]),
+        .O(o_ech_fct[20]));
+  CARRY4 \o_ech_fct[20]_INST_0_i_1 
+       (.CI(\o_ech_fct[16]_INST_0_i_1_n_0 ),
+        .CO({\o_ech_fct[20]_INST_0_i_1_n_0 ,\o_ech_fct[20]_INST_0_i_1_n_1 ,\o_ech_fct[20]_INST_0_i_1_n_2 ,\o_ech_fct[20]_INST_0_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O(plusOp[20:17]),
+        .S(p_0_in[20:17]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[20]_INST_0_i_2 
+       (.I0(\o_ech_fct[22]_INST_0_i_8_n_4 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[20]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[20]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[20]_INST_0_i_3 
+       (.I0(\o_ech_fct[22]_INST_0_i_8_n_5 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[19]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[19]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[20]_INST_0_i_4 
+       (.I0(\o_ech_fct[22]_INST_0_i_8_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[18]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[18]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[20]_INST_0_i_5 
+       (.I0(\o_ech_fct[22]_INST_0_i_8_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[17]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[17]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[21]_INST_0 
+       (.I0(plusOp[21]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[21]),
+        .O(o_ech_fct[21]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[22]_INST_0 
+       (.I0(plusOp[22]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[22]),
+        .O(o_ech_fct[22]));
+  LUT6 #(
+    .INIT(64'hF000FFFFF000E000)) 
+    \o_ech_fct[22]_INST_0_i_1 
+       (.I0(\o_ech_fct[22]_INST_0_i_2_n_0 ),
+        .I1(\o_ech_fct[22]_INST_0_i_3_n_0 ),
+        .I2(\o_ech_fct[22]_INST_0_i_4_n_5 ),
+        .I3(i_ech[23]),
+        .I4(\o_ech_fct[22]_INST_0_i_5_n_0 ),
+        .I5(\o_ech_fct[22]_INST_0_i_6_n_0 ),
+        .O(\o_ech_fct[22]_INST_0_i_1_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_10 
+       (.I0(i_ech[22]),
+        .O(\o_ech_fct[22]_INST_0_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_11 
+       (.I0(i_ech[21]),
+        .O(\o_ech_fct[22]_INST_0_i_11_n_0 ));
+  LUT4 #(
+    .INIT(16'hFFFE)) 
+    \o_ech_fct[22]_INST_0_i_12 
+       (.I0(i_ech[12]),
+        .I1(i_ech[13]),
+        .I2(i_ech[14]),
+        .I3(i_ech[15]),
+        .O(\o_ech_fct[22]_INST_0_i_12_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT4 #(
+    .INIT(16'hFFFE)) 
+    \o_ech_fct[22]_INST_0_i_13 
+       (.I0(i_ech[16]),
+        .I1(i_ech[17]),
+        .I2(i_ech[18]),
+        .I3(i_ech[19]),
+        .O(\o_ech_fct[22]_INST_0_i_13_n_0 ));
+  LUT4 #(
+    .INIT(16'hFFFE)) 
+    \o_ech_fct[22]_INST_0_i_14 
+       (.I0(i_ech[4]),
+        .I1(i_ech[5]),
+        .I2(i_ech[6]),
+        .I3(i_ech[7]),
+        .O(\o_ech_fct[22]_INST_0_i_14_n_0 ));
+  LUT4 #(
+    .INIT(16'h0001)) 
+    \o_ech_fct[22]_INST_0_i_15 
+       (.I0(i_ech[1]),
+        .I1(i_ech[0]),
+        .I2(i_ech[3]),
+        .I3(i_ech[2]),
+        .O(\o_ech_fct[22]_INST_0_i_15_n_0 ));
+  LUT2 #(
+    .INIT(4'h1)) 
+    \o_ech_fct[22]_INST_0_i_16 
+       (.I0(i_ech[20]),
+        .I1(i_ech[21]),
+        .O(\o_ech_fct[22]_INST_0_i_16_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_17 
+       (.I0(i_ech[20]),
+        .O(\o_ech_fct[22]_INST_0_i_17_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_18 
+       (.I0(i_ech[19]),
+        .O(\o_ech_fct[22]_INST_0_i_18_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_19 
+       (.I0(i_ech[18]),
+        .O(\o_ech_fct[22]_INST_0_i_19_n_0 ));
+  LUT6 #(
+    .INIT(64'hFFFFFFFFFFFEFFFF)) 
+    \o_ech_fct[22]_INST_0_i_2 
+       (.I0(i_ech[2]),
+        .I1(i_ech[1]),
+        .I2(i_ech[3]),
+        .I3(i_ech[22]),
+        .I4(i_ech[23]),
+        .I5(\o_ech_fct[22]_INST_0_i_7_n_0 ),
+        .O(\o_ech_fct[22]_INST_0_i_2_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_20 
+       (.I0(i_ech[17]),
+        .O(\o_ech_fct[22]_INST_0_i_20_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'hFFFFFFFE)) 
+    \o_ech_fct[22]_INST_0_i_3 
+       (.I0(i_ech[0]),
+        .I1(i_ech[19]),
+        .I2(i_ech[18]),
+        .I3(i_ech[17]),
+        .I4(i_ech[16]),
+        .O(\o_ech_fct[22]_INST_0_i_3_n_0 ));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[22]_INST_0_i_4 
+       (.CI(\o_ech_fct[22]_INST_0_i_8_n_0 ),
+        .CO({\NLW_o_ech_fct[22]_INST_0_i_4_CO_UNCONNECTED [3:2],\o_ech_fct[22]_INST_0_i_4_n_2 ,\o_ech_fct[22]_INST_0_i_4_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\NLW_o_ech_fct[22]_INST_0_i_4_O_UNCONNECTED [3],\o_ech_fct[22]_INST_0_i_4_n_5 ,\o_ech_fct[22]_INST_0_i_4_n_6 ,\o_ech_fct[22]_INST_0_i_4_n_7 }),
+        .S({1'b0,\o_ech_fct[22]_INST_0_i_9_n_0 ,\o_ech_fct[22]_INST_0_i_10_n_0 ,\o_ech_fct[22]_INST_0_i_11_n_0 }));
+  LUT5 #(
+    .INIT(32'hFFFFFFFE)) 
+    \o_ech_fct[22]_INST_0_i_5 
+       (.I0(i_ech[11]),
+        .I1(i_ech[10]),
+        .I2(i_ech[9]),
+        .I3(i_ech[8]),
+        .I4(\o_ech_fct[22]_INST_0_i_12_n_0 ),
+        .O(\o_ech_fct[22]_INST_0_i_5_n_0 ));
+  LUT6 #(
+    .INIT(64'h0010000000000000)) 
+    \o_ech_fct[22]_INST_0_i_6 
+       (.I0(\o_ech_fct[22]_INST_0_i_13_n_0 ),
+        .I1(\o_ech_fct[22]_INST_0_i_14_n_0 ),
+        .I2(\o_ech_fct[22]_INST_0_i_15_n_0 ),
+        .I3(i_ech[22]),
+        .I4(i_ech[23]),
+        .I5(\o_ech_fct[22]_INST_0_i_16_n_0 ),
+        .O(\o_ech_fct[22]_INST_0_i_6_n_0 ));
+  LUT6 #(
+    .INIT(64'hFFFFFFFFFFFFFFFE)) 
+    \o_ech_fct[22]_INST_0_i_7 
+       (.I0(i_ech[7]),
+        .I1(i_ech[6]),
+        .I2(i_ech[5]),
+        .I3(i_ech[4]),
+        .I4(i_ech[21]),
+        .I5(i_ech[20]),
+        .O(\o_ech_fct[22]_INST_0_i_7_n_0 ));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[22]_INST_0_i_8 
+       (.CI(\o_ech_fct[16]_INST_0_i_6_n_0 ),
+        .CO({\o_ech_fct[22]_INST_0_i_8_n_0 ,\o_ech_fct[22]_INST_0_i_8_n_1 ,\o_ech_fct[22]_INST_0_i_8_n_2 ,\o_ech_fct[22]_INST_0_i_8_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\o_ech_fct[22]_INST_0_i_8_n_4 ,\o_ech_fct[22]_INST_0_i_8_n_5 ,\o_ech_fct[22]_INST_0_i_8_n_6 ,\o_ech_fct[22]_INST_0_i_8_n_7 }),
+        .S({\o_ech_fct[22]_INST_0_i_17_n_0 ,\o_ech_fct[22]_INST_0_i_18_n_0 ,\o_ech_fct[22]_INST_0_i_19_n_0 ,\o_ech_fct[22]_INST_0_i_20_n_0 }));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[22]_INST_0_i_9 
+       (.I0(i_ech[23]),
+        .O(\o_ech_fct[22]_INST_0_i_9_n_0 ));
+  LUT2 #(
+    .INIT(4'h2)) 
+    \o_ech_fct[23]_INST_0 
+       (.I0(i_ech[23]),
+        .I1(\o_ech_fct[23]_INST_0_i_1_n_1 ),
+        .O(o_ech_fct[23]));
+  CARRY4 \o_ech_fct[23]_INST_0_i_1 
+       (.CI(\o_ech_fct[20]_INST_0_i_1_n_0 ),
+        .CO({\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED [3],\o_ech_fct[23]_INST_0_i_1_n_1 ,\NLW_o_ech_fct[23]_INST_0_i_1_CO_UNCONNECTED [1],\o_ech_fct[23]_INST_0_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\NLW_o_ech_fct[23]_INST_0_i_1_O_UNCONNECTED [3:2],plusOp[22:21]}),
+        .S({1'b0,1'b1,p_0_in[22:21]}));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[23]_INST_0_i_2 
+       (.I0(\o_ech_fct[22]_INST_0_i_4_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[22]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[22]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[23]_INST_0_i_3 
+       (.I0(\o_ech_fct[22]_INST_0_i_4_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[21]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[21]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[2]_INST_0 
+       (.I0(plusOp[2]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[2]),
+        .O(o_ech_fct[2]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[3]_INST_0 
+       (.I0(plusOp[3]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[3]),
+        .O(o_ech_fct[3]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[4]_INST_0 
+       (.I0(plusOp[4]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[4]),
+        .O(o_ech_fct[4]));
+  CARRY4 \o_ech_fct[4]_INST_0_i_1 
+       (.CI(1'b0),
+        .CO({\o_ech_fct[4]_INST_0_i_1_n_0 ,\o_ech_fct[4]_INST_0_i_1_n_1 ,\o_ech_fct[4]_INST_0_i_1_n_2 ,\o_ech_fct[4]_INST_0_i_1_n_3 }),
+        .CYINIT(p_0_in[0]),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O(plusOp[4:1]),
+        .S(p_0_in[4:1]));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[4]_INST_0_i_10 
+       (.I0(i_ech[3]),
+        .O(\o_ech_fct[4]_INST_0_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[4]_INST_0_i_11 
+       (.I0(i_ech[2]),
+        .O(\o_ech_fct[4]_INST_0_i_11_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[4]_INST_0_i_12 
+       (.I0(i_ech[1]),
+        .O(\o_ech_fct[4]_INST_0_i_12_n_0 ));
+  LUT2 #(
+    .INIT(4'h1)) 
+    \o_ech_fct[4]_INST_0_i_2 
+       (.I0(i_ech[0]),
+        .I1(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[0]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[4]_INST_0_i_3 
+       (.I0(\o_ech_fct[4]_INST_0_i_7_n_4 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[4]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[4]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[4]_INST_0_i_4 
+       (.I0(\o_ech_fct[4]_INST_0_i_7_n_5 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[3]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[3]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[4]_INST_0_i_5 
+       (.I0(\o_ech_fct[4]_INST_0_i_7_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[2]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[2]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[4]_INST_0_i_6 
+       (.I0(\o_ech_fct[4]_INST_0_i_7_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[1]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[1]));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[4]_INST_0_i_7 
+       (.CI(1'b0),
+        .CO({\o_ech_fct[4]_INST_0_i_7_n_0 ,\o_ech_fct[4]_INST_0_i_7_n_1 ,\o_ech_fct[4]_INST_0_i_7_n_2 ,\o_ech_fct[4]_INST_0_i_7_n_3 }),
+        .CYINIT(\o_ech_fct[4]_INST_0_i_8_n_0 ),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\o_ech_fct[4]_INST_0_i_7_n_4 ,\o_ech_fct[4]_INST_0_i_7_n_5 ,\o_ech_fct[4]_INST_0_i_7_n_6 ,\o_ech_fct[4]_INST_0_i_7_n_7 }),
+        .S({\o_ech_fct[4]_INST_0_i_9_n_0 ,\o_ech_fct[4]_INST_0_i_10_n_0 ,\o_ech_fct[4]_INST_0_i_11_n_0 ,\o_ech_fct[4]_INST_0_i_12_n_0 }));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[4]_INST_0_i_8 
+       (.I0(i_ech[0]),
+        .O(\o_ech_fct[4]_INST_0_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[4]_INST_0_i_9 
+       (.I0(i_ech[4]),
+        .O(\o_ech_fct[4]_INST_0_i_9_n_0 ));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[5]_INST_0 
+       (.I0(plusOp[5]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[5]),
+        .O(o_ech_fct[5]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[6]_INST_0 
+       (.I0(plusOp[6]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[6]),
+        .O(o_ech_fct[6]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[7]_INST_0 
+       (.I0(plusOp[7]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[7]),
+        .O(o_ech_fct[7]));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[8]_INST_0 
+       (.I0(plusOp[8]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[8]),
+        .O(o_ech_fct[8]));
+  CARRY4 \o_ech_fct[8]_INST_0_i_1 
+       (.CI(\o_ech_fct[4]_INST_0_i_1_n_0 ),
+        .CO({\o_ech_fct[8]_INST_0_i_1_n_0 ,\o_ech_fct[8]_INST_0_i_1_n_1 ,\o_ech_fct[8]_INST_0_i_1_n_2 ,\o_ech_fct[8]_INST_0_i_1_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O(plusOp[8:5]),
+        .S(p_0_in[8:5]));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[8]_INST_0_i_10 
+       (.I0(i_ech[5]),
+        .O(\o_ech_fct[8]_INST_0_i_10_n_0 ));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[8]_INST_0_i_2 
+       (.I0(\o_ech_fct[8]_INST_0_i_6_n_4 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[8]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[8]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[8]_INST_0_i_3 
+       (.I0(\o_ech_fct[8]_INST_0_i_6_n_5 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[7]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[7]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[8]_INST_0_i_4 
+       (.I0(\o_ech_fct[8]_INST_0_i_6_n_6 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[6]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[6]));
+  LUT4 #(
+    .INIT(16'h0047)) 
+    \o_ech_fct[8]_INST_0_i_5 
+       (.I0(\o_ech_fct[8]_INST_0_i_6_n_7 ),
+        .I1(i_ech[23]),
+        .I2(i_ech[5]),
+        .I3(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .O(p_0_in[5]));
+  (* ADDER_THRESHOLD = "35" *) 
+  CARRY4 \o_ech_fct[8]_INST_0_i_6 
+       (.CI(\o_ech_fct[4]_INST_0_i_7_n_0 ),
+        .CO({\o_ech_fct[8]_INST_0_i_6_n_0 ,\o_ech_fct[8]_INST_0_i_6_n_1 ,\o_ech_fct[8]_INST_0_i_6_n_2 ,\o_ech_fct[8]_INST_0_i_6_n_3 }),
+        .CYINIT(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0}),
+        .O({\o_ech_fct[8]_INST_0_i_6_n_4 ,\o_ech_fct[8]_INST_0_i_6_n_5 ,\o_ech_fct[8]_INST_0_i_6_n_6 ,\o_ech_fct[8]_INST_0_i_6_n_7 }),
+        .S({\o_ech_fct[8]_INST_0_i_7_n_0 ,\o_ech_fct[8]_INST_0_i_8_n_0 ,\o_ech_fct[8]_INST_0_i_9_n_0 ,\o_ech_fct[8]_INST_0_i_10_n_0 }));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[8]_INST_0_i_7 
+       (.I0(i_ech[8]),
+        .O(\o_ech_fct[8]_INST_0_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[8]_INST_0_i_8 
+       (.I0(i_ech[7]),
+        .O(\o_ech_fct[8]_INST_0_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2'h1)) 
+    \o_ech_fct[8]_INST_0_i_9 
+       (.I0(i_ech[6]),
+        .O(\o_ech_fct[8]_INST_0_i_9_n_0 ));
+  LUT4 #(
+    .INIT(16'hBBB8)) 
+    \o_ech_fct[9]_INST_0 
+       (.I0(plusOp[9]),
+        .I1(i_ech[23]),
+        .I2(\o_ech_fct[22]_INST_0_i_1_n_0 ),
+        .I3(i_ech[9]),
+        .O(o_ech_fct[9]));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v
new file mode 100644
index 0000000..55b1bdc
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v
@@ -0,0 +1,21 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

+// --------------------------------------------------------------------------------

+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020

+// Date        : Tue Jan 16 12:03:16 2024

+// Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)

+// Command     : write_verilog -force -mode synth_stub

+//               c:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0_stub.v

+// Design      : design_1_sig_fct_sat_dure_0_0

+// Purpose     : Stub declaration of top-level module interface

+// Device      : xc7z010clg400-1

+// --------------------------------------------------------------------------------

+

+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

+// Please paste the declaration into a Verilog source file or add the file as an additional source.

+(* x_core_info = "sig_fct_sat_dure,Vivado 2020.2" *)

+module design_1_sig_fct_sat_dure_0_0(i_ech, o_ech_fct)

+/* synthesis syn_black_box black_box_pad_pin="i_ech[23:0],o_ech_fct[23:0]" */;

+  input [23:0]i_ech;

+  output [23:0]o_ech_fct;

+endmodule

diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
new file mode 100644
index 0000000..27c63d5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_0;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"7FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd
new file mode 100644
index 0000000..9b42275
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/synth/design_1_sig_fct_sat_dure_0_0.vhd
@@ -0,0 +1,92 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_0;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "sig_fct_sat_dure,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_sat_dure_0_0_arch : ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_0,sig_fct_sat_dure,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_sat_dure,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_ech_u24_max=0x7FFFFF}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"7FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_0_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml
new file mode 100644
index 0000000..07731a7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xml
@@ -0,0 +1,219 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_sig_fct_sat_dure_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>sig_fct_sat_dure</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:9a3245c3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_sig_fct_sat_dure_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:9a3245c3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>sig_fct_sat_dure</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:168f8b75</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:168f8b75</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>design_1_sig_fct_sat_dure_0_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:168f8b75</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:168f8b75</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="unsigned(23 downto 0)">
+        <spirit:name>c_ech_u24_max</spirit:name>
+        <spirit:displayName>C Ech U24 Max</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_sig_fct_sat_dure_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_sig_fct_sat_dure_0_1.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_1.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_1_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_1_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_1_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_sig_fct_sat_dure_0_1_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:sig_fct_sat_dure:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>c_ech_u24_max</spirit:name>
+      <spirit:displayName>C Ech U24 Max</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_sig_fct_sat_dure_0_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>sig_fct_sat_dure_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
new file mode 100644
index 0000000..b557a37
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_1 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_1;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"1FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd
new file mode 100644
index 0000000..51b2616
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/synth/design_1_sig_fct_sat_dure_0_1.vhd
@@ -0,0 +1,92 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_1 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_1;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "sig_fct_sat_dure,Vivado 2020.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_sig_fct_sat_dure_0_1_arch : ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_1,sig_fct_sat_dure,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "design_1_sig_fct_sat_dure_0_1,sig_fct_sat_dure,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sig_fct_sat_dure,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_ech_u24_max=0x1FFFFF}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"1FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_1_arch;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml
new file mode 100644
index 0000000..370f24f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xml
@@ -0,0 +1,320 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_util_vector_logic_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+        <spirit:displayName>Verilog Simulation</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>util_vector_logic_v2_0_1_util_vector_logic</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f5f3e7cb</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
+        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_util_vector_logic_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f5f3e7cb</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>util_vector_logic_v2_0_1_util_vector_logic</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
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+          <spirit:parameter>
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+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:0c521749</spirit:value>
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+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_util_vector_logic_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
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+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
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+            <spirit:value>9:0c521749</spirit:value>
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+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Op1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Op2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Op2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_OPERATION&apos;)) != &apos;not&apos;)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Res</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_OPERATION</spirit:name>
+        <spirit:displayName>C Operation</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPERATION">or</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SIZE</spirit:name>
+        <spirit:displayName>C Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIZE">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_e94027ef</spirit:name>
+      <spirit:enumeration>and</spirit:enumeration>
+      <spirit:enumeration>or</spirit:enumeration>
+      <spirit:enumeration>xor</spirit:enumeration>
+      <spirit:enumeration>not</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>util_vector_logic_v2_0_1</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_util_vector_logic_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>util_vector_logic_v2_0_1</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_util_vector_logic_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>design_1_util_vector_logic_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_util_vector_logic_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_util_vector_logic_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_util_vector_logic_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>design_1_util_vector_logic_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_util_vector_logic_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_SIZE</spirit:name>
+      <spirit:displayName>C_SIZE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SIZE" spirit:order="3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPERATION</spirit:name>
+      <spirit:displayName>C_OPERATION</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPERATION" spirit:choiceRef="choice_list_e94027ef" spirit:order="4">or</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOGO_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOGO_FILE" spirit:order="5">data/sym_orgate.png</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.LOGO_FILE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Utility Vector Logic</xilinx:displayName>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_OPERATION" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SIZE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOGO_FILE" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8ba71b33"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="99e4b00a"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="426d7563"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="80130fcb"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
new file mode 100644
index 0000000..c3f6299
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
@@ -0,0 +1,74 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_util_vector_logic_0_0 (
+  Op1,
+  Op2,
+  Res
+);
+
+input wire [0 : 0] Op1;
+input wire [0 : 0] Op2;
+output wire [0 : 0] Res;
+
+  util_vector_logic_v2_0_1_util_vector_logic #(
+    .C_OPERATION("or"),
+    .C_SIZE(1)
+  ) inst (
+    .Op1(Op1),
+    .Op2(Op2),
+    .Res(Res)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v
new file mode 100644
index 0000000..7d09a63
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/synth/design_1_util_vector_logic_0_0.v
@@ -0,0 +1,75 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
+// IP Revision: 1
+
+(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *)
+(* CORE_GENERATION_INFO = "design_1_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_util_vector_logic_0_0 (
+  Op1,
+  Op2,
+  Res
+);
+
+input wire [0 : 0] Op1;
+input wire [0 : 0] Op2;
+output wire [0 : 0] Res;
+
+  util_vector_logic_v2_0_1_util_vector_logic #(
+    .C_OPERATION("or"),
+    .C_SIZE(1)
+  ) inst (
+    .Op1(Op1),
+    .Op2(Op2),
+    .Res(Res)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml
new file mode 100644
index 0000000..d5d682f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xml
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_util_vector_logic_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Op1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Op2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Op2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_OPERATION&apos;)) != &apos;not&apos;)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Res</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_OPERATION</spirit:name>
+        <spirit:displayName>C Operation</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPERATION">or</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SIZE</spirit:name>
+        <spirit:displayName>C Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIZE">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_e94027ef</spirit:name>
+      <spirit:enumeration>and</spirit:enumeration>
+      <spirit:enumeration>or</spirit:enumeration>
+      <spirit:enumeration>xor</spirit:enumeration>
+      <spirit:enumeration>not</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Performs bitwise logic operations on two n-bit inputs to produce a single n-bit output</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_util_vector_logic_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_SIZE</spirit:name>
+      <spirit:displayName>C_SIZE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SIZE" spirit:order="3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPERATION</spirit:name>
+      <spirit:displayName>C_OPERATION</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPERATION" spirit:choiceRef="choice_list_e94027ef" spirit:order="4">or</spirit:value>
+    </spirit:parameter>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml
new file mode 100644
index 0000000..6c0d417
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xml
@@ -0,0 +1,5065 @@
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN27_WIDTH</spirit:name>
+        <spirit:displayName>In27 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN27_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN28_WIDTH</spirit:name>
+        <spirit:displayName>In28 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN28_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN29_WIDTH</spirit:name>
+        <spirit:displayName>In29 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN29_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN30_WIDTH</spirit:name>
+        <spirit:displayName>In30 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN30_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN31_WIDTH</spirit:name>
+        <spirit:displayName>In31 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN31_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN32_WIDTH</spirit:name>
+        <spirit:displayName>In32 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN32_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN33_WIDTH</spirit:name>
+        <spirit:displayName>In33 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN33_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN34_WIDTH</spirit:name>
+        <spirit:displayName>In34 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN34_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN35_WIDTH</spirit:name>
+        <spirit:displayName>In35 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN35_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN36_WIDTH</spirit:name>
+        <spirit:displayName>In36 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN36_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN37_WIDTH</spirit:name>
+        <spirit:displayName>In37 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN37_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN38_WIDTH</spirit:name>
+        <spirit:displayName>In38 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN38_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN39_WIDTH</spirit:name>
+        <spirit:displayName>In39 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN39_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN40_WIDTH</spirit:name>
+        <spirit:displayName>In40 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN40_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN41_WIDTH</spirit:name>
+        <spirit:displayName>In41 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN41_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN42_WIDTH</spirit:name>
+        <spirit:displayName>In42 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN42_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN43_WIDTH</spirit:name>
+        <spirit:displayName>In43 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN43_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN44_WIDTH</spirit:name>
+        <spirit:displayName>In44 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN44_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN45_WIDTH</spirit:name>
+        <spirit:displayName>In45 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN45_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN46_WIDTH</spirit:name>
+        <spirit:displayName>In46 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN46_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN47_WIDTH</spirit:name>
+        <spirit:displayName>In47 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN47_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN48_WIDTH</spirit:name>
+        <spirit:displayName>In48 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN48_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN49_WIDTH</spirit:name>
+        <spirit:displayName>In49 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN49_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN50_WIDTH</spirit:name>
+        <spirit:displayName>In50 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN50_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN51_WIDTH</spirit:name>
+        <spirit:displayName>In51 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN51_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN52_WIDTH</spirit:name>
+        <spirit:displayName>In52 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN52_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN53_WIDTH</spirit:name>
+        <spirit:displayName>In53 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN53_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN54_WIDTH</spirit:name>
+        <spirit:displayName>In54 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN54_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN55_WIDTH</spirit:name>
+        <spirit:displayName>In55 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN55_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN56_WIDTH</spirit:name>
+        <spirit:displayName>In56 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN56_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN57_WIDTH</spirit:name>
+        <spirit:displayName>In57 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN57_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN58_WIDTH</spirit:name>
+        <spirit:displayName>In58 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN58_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN59_WIDTH</spirit:name>
+        <spirit:displayName>In59 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN59_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN60_WIDTH</spirit:name>
+        <spirit:displayName>In60 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN60_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN61_WIDTH</spirit:name>
+        <spirit:displayName>In61 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN61_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN62_WIDTH</spirit:name>
+        <spirit:displayName>In62 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN62_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN63_WIDTH</spirit:name>
+        <spirit:displayName>In63 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN63_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN64_WIDTH</spirit:name>
+        <spirit:displayName>In64 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN64_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN65_WIDTH</spirit:name>
+        <spirit:displayName>In65 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN65_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN66_WIDTH</spirit:name>
+        <spirit:displayName>In66 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN66_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN67_WIDTH</spirit:name>
+        <spirit:displayName>In67 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN67_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN68_WIDTH</spirit:name>
+        <spirit:displayName>In68 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN68_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN69_WIDTH</spirit:name>
+        <spirit:displayName>In69 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN69_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN70_WIDTH</spirit:name>
+        <spirit:displayName>In70 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN70_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN71_WIDTH</spirit:name>
+        <spirit:displayName>In71 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN71_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN72_WIDTH</spirit:name>
+        <spirit:displayName>In72 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN72_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN73_WIDTH</spirit:name>
+        <spirit:displayName>In73 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN73_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN74_WIDTH</spirit:name>
+        <spirit:displayName>In74 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN74_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN75_WIDTH</spirit:name>
+        <spirit:displayName>In75 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN75_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN76_WIDTH</spirit:name>
+        <spirit:displayName>In76 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN76_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN77_WIDTH</spirit:name>
+        <spirit:displayName>In77 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN77_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN78_WIDTH</spirit:name>
+        <spirit:displayName>In78 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN78_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN79_WIDTH</spirit:name>
+        <spirit:displayName>In79 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN79_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN80_WIDTH</spirit:name>
+        <spirit:displayName>In80 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN80_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN81_WIDTH</spirit:name>
+        <spirit:displayName>In81 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN81_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN82_WIDTH</spirit:name>
+        <spirit:displayName>In82 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN82_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN83_WIDTH</spirit:name>
+        <spirit:displayName>In83 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN83_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN84_WIDTH</spirit:name>
+        <spirit:displayName>In84 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN84_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN85_WIDTH</spirit:name>
+        <spirit:displayName>In85 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN85_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN86_WIDTH</spirit:name>
+        <spirit:displayName>In86 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN86_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN87_WIDTH</spirit:name>
+        <spirit:displayName>In87 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN87_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN88_WIDTH</spirit:name>
+        <spirit:displayName>In88 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN88_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN89_WIDTH</spirit:name>
+        <spirit:displayName>In89 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN89_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN90_WIDTH</spirit:name>
+        <spirit:displayName>In90 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN90_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN91_WIDTH</spirit:name>
+        <spirit:displayName>In91 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN91_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN92_WIDTH</spirit:name>
+        <spirit:displayName>In92 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN92_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN93_WIDTH</spirit:name>
+        <spirit:displayName>In93 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN93_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN94_WIDTH</spirit:name>
+        <spirit:displayName>In94 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN94_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN95_WIDTH</spirit:name>
+        <spirit:displayName>In95 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN95_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN96_WIDTH</spirit:name>
+        <spirit:displayName>In96 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN96_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN97_WIDTH</spirit:name>
+        <spirit:displayName>In97 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN97_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN98_WIDTH</spirit:name>
+        <spirit:displayName>In98 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN98_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN99_WIDTH</spirit:name>
+        <spirit:displayName>In99 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN99_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN100_WIDTH</spirit:name>
+        <spirit:displayName>In100 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN100_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN101_WIDTH</spirit:name>
+        <spirit:displayName>In101 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN101_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN102_WIDTH</spirit:name>
+        <spirit:displayName>In102 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN102_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN103_WIDTH</spirit:name>
+        <spirit:displayName>In103 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN103_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN104_WIDTH</spirit:name>
+        <spirit:displayName>In104 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN104_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN105_WIDTH</spirit:name>
+        <spirit:displayName>In105 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN105_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN106_WIDTH</spirit:name>
+        <spirit:displayName>In106 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN106_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN107_WIDTH</spirit:name>
+        <spirit:displayName>In107 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN107_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN108_WIDTH</spirit:name>
+        <spirit:displayName>In108 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN108_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN109_WIDTH</spirit:name>
+        <spirit:displayName>In109 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN109_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN110_WIDTH</spirit:name>
+        <spirit:displayName>In110 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN110_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN111_WIDTH</spirit:name>
+        <spirit:displayName>In111 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN111_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN112_WIDTH</spirit:name>
+        <spirit:displayName>In112 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN112_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN113_WIDTH</spirit:name>
+        <spirit:displayName>In113 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN113_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN114_WIDTH</spirit:name>
+        <spirit:displayName>In114 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN114_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN115_WIDTH</spirit:name>
+        <spirit:displayName>In115 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN115_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN116_WIDTH</spirit:name>
+        <spirit:displayName>In116 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN116_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN117_WIDTH</spirit:name>
+        <spirit:displayName>In117 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN117_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN118_WIDTH</spirit:name>
+        <spirit:displayName>In118 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN118_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN119_WIDTH</spirit:name>
+        <spirit:displayName>In119 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN119_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN120_WIDTH</spirit:name>
+        <spirit:displayName>In120 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN120_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN121_WIDTH</spirit:name>
+        <spirit:displayName>In121 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN121_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN122_WIDTH</spirit:name>
+        <spirit:displayName>In122 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN122_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN123_WIDTH</spirit:name>
+        <spirit:displayName>In123 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN123_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN124_WIDTH</spirit:name>
+        <spirit:displayName>In124 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN124_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN125_WIDTH</spirit:name>
+        <spirit:displayName>In125 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN125_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN126_WIDTH</spirit:name>
+        <spirit:displayName>In126 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN126_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN127_WIDTH</spirit:name>
+        <spirit:displayName>In127 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN127_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>dout_width</spirit:name>
+        <spirit:displayName>Dout Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.dout_width">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_PORTS</spirit:name>
+        <spirit:displayName>Number of Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PORTS">2</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>xlconcat_v2_1_4</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconcat_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xlconcat_v2_1_4</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_xlconcat_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Concatenates up to 128 ports into a single port</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconcat_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>NUM_PORTS</spirit:name>
+      <spirit:displayName>Number of Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PORTS" spirit:order="3" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN0_WIDTH</spirit:name>
+      <spirit:displayName>In0 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN0_WIDTH" spirit:order="4" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN1_WIDTH</spirit:name>
+      <spirit:displayName>In1 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN1_WIDTH" spirit:order="5" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN2_WIDTH</spirit:name>
+      <spirit:displayName>In2 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN2_WIDTH" spirit:order="6" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN3_WIDTH</spirit:name>
+      <spirit:displayName>In3 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN3_WIDTH" spirit:order="7" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN4_WIDTH</spirit:name>
+      <spirit:displayName>In4 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN4_WIDTH" spirit:order="8" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN5_WIDTH</spirit:name>
+      <spirit:displayName>In5 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN5_WIDTH" spirit:order="9" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN6_WIDTH</spirit:name>
+      <spirit:displayName>In6 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN6_WIDTH" spirit:order="10" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN7_WIDTH</spirit:name>
+      <spirit:displayName>In7 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN7_WIDTH" spirit:order="11" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN8_WIDTH</spirit:name>
+      <spirit:displayName>In8 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN8_WIDTH" spirit:order="12" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN9_WIDTH</spirit:name>
+      <spirit:displayName>In9 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN9_WIDTH" spirit:order="13" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN10_WIDTH</spirit:name>
+      <spirit:displayName>In10 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN10_WIDTH" spirit:order="14" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN11_WIDTH</spirit:name>
+      <spirit:displayName>In11 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN11_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN12_WIDTH</spirit:name>
+      <spirit:displayName>In12 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN12_WIDTH" spirit:order="16" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN13_WIDTH</spirit:name>
+      <spirit:displayName>In13 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN13_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN14_WIDTH</spirit:name>
+      <spirit:displayName>In14 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN14_WIDTH" spirit:order="18" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN15_WIDTH</spirit:name>
+      <spirit:displayName>In15 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN15_WIDTH" spirit:order="19" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN16_WIDTH</spirit:name>
+      <spirit:displayName>In16 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN16_WIDTH" spirit:order="20" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN17_WIDTH</spirit:name>
+      <spirit:displayName>In17 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN17_WIDTH" spirit:order="21" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN18_WIDTH</spirit:name>
+      <spirit:displayName>In18 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN18_WIDTH" spirit:order="22" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN19_WIDTH</spirit:name>
+      <spirit:displayName>In19 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN19_WIDTH" spirit:order="23" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN20_WIDTH</spirit:name>
+      <spirit:displayName>In20 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN20_WIDTH" spirit:order="24" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN21_WIDTH</spirit:name>
+      <spirit:displayName>In21 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN21_WIDTH" spirit:order="25" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN22_WIDTH</spirit:name>
+      <spirit:displayName>In22 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN22_WIDTH" spirit:order="26" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN23_WIDTH</spirit:name>
+      <spirit:displayName>In23 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN23_WIDTH" spirit:order="27" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN24_WIDTH</spirit:name>
+      <spirit:displayName>In24 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN24_WIDTH" spirit:order="28" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN25_WIDTH</spirit:name>
+      <spirit:displayName>In25 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN25_WIDTH" spirit:order="29" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN26_WIDTH</spirit:name>
+      <spirit:displayName>In26 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN26_WIDTH" spirit:order="30" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN27_WIDTH</spirit:name>
+      <spirit:displayName>In27 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN27_WIDTH" spirit:order="31" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN28_WIDTH</spirit:name>
+      <spirit:displayName>In28 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN28_WIDTH" spirit:order="32" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN29_WIDTH</spirit:name>
+      <spirit:displayName>In29 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN29_WIDTH" spirit:order="33" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN30_WIDTH</spirit:name>
+      <spirit:displayName>In30 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN30_WIDTH" spirit:order="34" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN31_WIDTH</spirit:name>
+      <spirit:displayName>In31 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN31_WIDTH" spirit:order="35" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN32_WIDTH</spirit:name>
+      <spirit:displayName>In32 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN32_WIDTH" spirit:order="36" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN33_WIDTH</spirit:name>
+      <spirit:displayName>In33 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN33_WIDTH" spirit:order="37" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN34_WIDTH</spirit:name>
+      <spirit:displayName>In34 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN34_WIDTH" spirit:order="38" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN35_WIDTH</spirit:name>
+      <spirit:displayName>In35 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN35_WIDTH" spirit:order="39" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN36_WIDTH</spirit:name>
+      <spirit:displayName>In36 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN36_WIDTH" spirit:order="40" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN37_WIDTH</spirit:name>
+      <spirit:displayName>In37 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN37_WIDTH" spirit:order="41" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN38_WIDTH</spirit:name>
+      <spirit:displayName>In38 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN38_WIDTH" spirit:order="42" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN39_WIDTH</spirit:name>
+      <spirit:displayName>In39 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN39_WIDTH" spirit:order="43" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN40_WIDTH</spirit:name>
+      <spirit:displayName>In40 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN40_WIDTH" spirit:order="44" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN41_WIDTH</spirit:name>
+      <spirit:displayName>In41 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN41_WIDTH" spirit:order="45" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN42_WIDTH</spirit:name>
+      <spirit:displayName>In42 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN42_WIDTH" spirit:order="46" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN43_WIDTH</spirit:name>
+      <spirit:displayName>In43 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN43_WIDTH" spirit:order="47" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN44_WIDTH</spirit:name>
+      <spirit:displayName>In44 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN44_WIDTH" spirit:order="48" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN45_WIDTH</spirit:name>
+      <spirit:displayName>In45 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN45_WIDTH" spirit:order="49" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN46_WIDTH</spirit:name>
+      <spirit:displayName>In46 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN46_WIDTH" spirit:order="50" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN47_WIDTH</spirit:name>
+      <spirit:displayName>In47 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN47_WIDTH" spirit:order="51" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN48_WIDTH</spirit:name>
+      <spirit:displayName>In48 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN48_WIDTH" spirit:order="52" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN49_WIDTH</spirit:name>
+      <spirit:displayName>In49 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN49_WIDTH" spirit:order="53" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN50_WIDTH</spirit:name>
+      <spirit:displayName>In50 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN50_WIDTH" spirit:order="54" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN51_WIDTH</spirit:name>
+      <spirit:displayName>In51 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN51_WIDTH" spirit:order="55" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN52_WIDTH</spirit:name>
+      <spirit:displayName>In52 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN52_WIDTH" spirit:order="56" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN53_WIDTH</spirit:name>
+      <spirit:displayName>In53 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN53_WIDTH" spirit:order="57" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN54_WIDTH</spirit:name>
+      <spirit:displayName>In54 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN54_WIDTH" spirit:order="58" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN55_WIDTH</spirit:name>
+      <spirit:displayName>In55 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN55_WIDTH" spirit:order="60" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN56_WIDTH</spirit:name>
+      <spirit:displayName>In56 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN56_WIDTH" spirit:order="61" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN57_WIDTH</spirit:name>
+      <spirit:displayName>In57 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN57_WIDTH" spirit:order="62" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN58_WIDTH</spirit:name>
+      <spirit:displayName>In58 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN58_WIDTH" spirit:order="63" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN59_WIDTH</spirit:name>
+      <spirit:displayName>In59 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN59_WIDTH" spirit:order="64" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN60_WIDTH</spirit:name>
+      <spirit:displayName>In60 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN60_WIDTH" spirit:order="65" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN61_WIDTH</spirit:name>
+      <spirit:displayName>In61 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN61_WIDTH" spirit:order="66" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN62_WIDTH</spirit:name>
+      <spirit:displayName>In62 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN62_WIDTH" spirit:order="67" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN63_WIDTH</spirit:name>
+      <spirit:displayName>In63 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN63_WIDTH" spirit:order="68" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN64_WIDTH</spirit:name>
+      <spirit:displayName>In64 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN64_WIDTH" spirit:order="69" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN65_WIDTH</spirit:name>
+      <spirit:displayName>In65 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN65_WIDTH" spirit:order="70" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN66_WIDTH</spirit:name>
+      <spirit:displayName>In66 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN66_WIDTH" spirit:order="71" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN67_WIDTH</spirit:name>
+      <spirit:displayName>In67 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN67_WIDTH" spirit:order="72" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN68_WIDTH</spirit:name>
+      <spirit:displayName>In68 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN68_WIDTH" spirit:order="73" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN69_WIDTH</spirit:name>
+      <spirit:displayName>In69 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN69_WIDTH" spirit:order="74" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN70_WIDTH</spirit:name>
+      <spirit:displayName>In70 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN70_WIDTH" spirit:order="75" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN71_WIDTH</spirit:name>
+      <spirit:displayName>In71 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN71_WIDTH" spirit:order="76" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN72_WIDTH</spirit:name>
+      <spirit:displayName>In72 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN72_WIDTH" spirit:order="77" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN73_WIDTH</spirit:name>
+      <spirit:displayName>In73 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN73_WIDTH" spirit:order="78" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN74_WIDTH</spirit:name>
+      <spirit:displayName>In74 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN74_WIDTH" spirit:order="79" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN75_WIDTH</spirit:name>
+      <spirit:displayName>In75 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN75_WIDTH" spirit:order="80" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN76_WIDTH</spirit:name>
+      <spirit:displayName>In76 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN76_WIDTH" spirit:order="81" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN77_WIDTH</spirit:name>
+      <spirit:displayName>In77 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN77_WIDTH" spirit:order="83" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN78_WIDTH</spirit:name>
+      <spirit:displayName>In78 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN78_WIDTH" spirit:order="84" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN79_WIDTH</spirit:name>
+      <spirit:displayName>In79 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN79_WIDTH" spirit:order="85" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN80_WIDTH</spirit:name>
+      <spirit:displayName>In80 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN80_WIDTH" spirit:order="86" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN81_WIDTH</spirit:name>
+      <spirit:displayName>In81 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN81_WIDTH" spirit:order="87" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN82_WIDTH</spirit:name>
+      <spirit:displayName>In82 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN82_WIDTH" spirit:order="88" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN83_WIDTH</spirit:name>
+      <spirit:displayName>In83 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN83_WIDTH" spirit:order="89" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN84_WIDTH</spirit:name>
+      <spirit:displayName>In84 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN84_WIDTH" spirit:order="90" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN85_WIDTH</spirit:name>
+      <spirit:displayName>In85 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN85_WIDTH" spirit:order="91" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN86_WIDTH</spirit:name>
+      <spirit:displayName>In86 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN86_WIDTH" spirit:order="92" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN87_WIDTH</spirit:name>
+      <spirit:displayName>In87 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN87_WIDTH" spirit:order="93" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN88_WIDTH</spirit:name>
+      <spirit:displayName>In88 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN88_WIDTH" spirit:order="94" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN89_WIDTH</spirit:name>
+      <spirit:displayName>In89 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN89_WIDTH" spirit:order="95" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN90_WIDTH</spirit:name>
+      <spirit:displayName>In90 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN90_WIDTH" spirit:order="96" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN91_WIDTH</spirit:name>
+      <spirit:displayName>In91 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN91_WIDTH" spirit:order="97" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN92_WIDTH</spirit:name>
+      <spirit:displayName>In92 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN92_WIDTH" spirit:order="98" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN93_WIDTH</spirit:name>
+      <spirit:displayName>In93 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN93_WIDTH" spirit:order="99" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN94_WIDTH</spirit:name>
+      <spirit:displayName>In94 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN94_WIDTH" spirit:order="100" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN95_WIDTH</spirit:name>
+      <spirit:displayName>In95 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN95_WIDTH" spirit:order="101" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN96_WIDTH</spirit:name>
+      <spirit:displayName>In96 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN96_WIDTH" spirit:order="102" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN97_WIDTH</spirit:name>
+      <spirit:displayName>In97 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN97_WIDTH" spirit:order="103" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN98_WIDTH</spirit:name>
+      <spirit:displayName>In98 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN98_WIDTH" spirit:order="104" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN99_WIDTH</spirit:name>
+      <spirit:displayName>In99 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN99_WIDTH" spirit:order="105" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN100_WIDTH</spirit:name>
+      <spirit:displayName>In100 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN100_WIDTH" spirit:order="106" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN101_WIDTH</spirit:name>
+      <spirit:displayName>In101 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN101_WIDTH" spirit:order="107" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN102_WIDTH</spirit:name>
+      <spirit:displayName>In102 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN102_WIDTH" spirit:order="108" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN103_WIDTH</spirit:name>
+      <spirit:displayName>In103 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN103_WIDTH" spirit:order="109" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN104_WIDTH</spirit:name>
+      <spirit:displayName>In104 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN104_WIDTH" spirit:order="110" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN105_WIDTH</spirit:name>
+      <spirit:displayName>In105 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN105_WIDTH" spirit:order="111" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN106_WIDTH</spirit:name>
+      <spirit:displayName>In106 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN106_WIDTH" spirit:order="112" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN107_WIDTH</spirit:name>
+      <spirit:displayName>In107 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN107_WIDTH" spirit:order="113" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN108_WIDTH</spirit:name>
+      <spirit:displayName>In108 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN108_WIDTH" spirit:order="114" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN109_WIDTH</spirit:name>
+      <spirit:displayName>In109 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN109_WIDTH" spirit:order="115" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN110_WIDTH</spirit:name>
+      <spirit:displayName>In110 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN110_WIDTH" spirit:order="116" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN111_WIDTH</spirit:name>
+      <spirit:displayName>In111 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN111_WIDTH" spirit:order="117" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN112_WIDTH</spirit:name>
+      <spirit:displayName>In112 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN112_WIDTH" spirit:order="118" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN113_WIDTH</spirit:name>
+      <spirit:displayName>In113 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN113_WIDTH" spirit:order="119" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN114_WIDTH</spirit:name>
+      <spirit:displayName>In114 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN114_WIDTH" spirit:order="120" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN115_WIDTH</spirit:name>
+      <spirit:displayName>In115 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN115_WIDTH" spirit:order="121" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN116_WIDTH</spirit:name>
+      <spirit:displayName>In116 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN116_WIDTH" spirit:order="122" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN117_WIDTH</spirit:name>
+      <spirit:displayName>In117 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN117_WIDTH" spirit:order="123" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN118_WIDTH</spirit:name>
+      <spirit:displayName>In118 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN118_WIDTH" spirit:order="124" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN119_WIDTH</spirit:name>
+      <spirit:displayName>In119 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN119_WIDTH" spirit:order="125" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN120_WIDTH</spirit:name>
+      <spirit:displayName>In120 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN120_WIDTH" spirit:order="126" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN121_WIDTH</spirit:name>
+      <spirit:displayName>In121 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN121_WIDTH" spirit:order="127" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN122_WIDTH</spirit:name>
+      <spirit:displayName>In122 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN122_WIDTH" spirit:order="128" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN123_WIDTH</spirit:name>
+      <spirit:displayName>In123 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN123_WIDTH" spirit:order="129" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN124_WIDTH</spirit:name>
+      <spirit:displayName>In124 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN124_WIDTH" spirit:order="130" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN125_WIDTH</spirit:name>
+      <spirit:displayName>In125 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN125_WIDTH" spirit:order="131" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN126_WIDTH</spirit:name>
+      <spirit:displayName>In126 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN126_WIDTH" spirit:order="132" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN127_WIDTH</spirit:name>
+      <spirit:displayName>In127 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN127_WIDTH" spirit:order="133" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dout_width</spirit:name>
+      <spirit:displayName>Dout Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.dout_width" spirit:order="134">2</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Concat</xilinx:displayName>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN0_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN100_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN101_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN102_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN103_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN104_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN105_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN106_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN107_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN108_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN109_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN10_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN110_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN111_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN112_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN113_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN114_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN115_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN116_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN117_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN118_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN119_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN11_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN120_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN121_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN122_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN123_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN124_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN125_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN126_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN127_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN12_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN13_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN14_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN15_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN16_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN17_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN18_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN19_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN1_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN20_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN21_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN22_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN23_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN24_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN25_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN26_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN27_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN28_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN29_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN2_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN30_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN31_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN32_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN33_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN34_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN35_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN36_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN37_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN38_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN39_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN3_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN40_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN41_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN42_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN43_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN44_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN45_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN46_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN47_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN48_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN49_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN4_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN50_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN51_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN52_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN53_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN54_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN55_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN56_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN57_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN58_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN59_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN5_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN60_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN61_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN62_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN63_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN64_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN65_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN66_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN67_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN68_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN69_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN6_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN70_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN71_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN72_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN73_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN74_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN75_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN76_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN77_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN78_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN79_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN7_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN80_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN81_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN82_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN83_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN84_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN85_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN86_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN87_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN88_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN89_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN8_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN90_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN91_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN92_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN93_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN94_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN95_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN96_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN97_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN98_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN99_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN9_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dout_width" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="898de776"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="8b4a6757"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="98f465e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="d6d5f6aa"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
new file mode 100644
index 0000000..25b5d97
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
@@ -0,0 +1,328 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconcat_0_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v
new file mode 100644
index 0000000..96ea47b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/synth/design_1_xlconcat_0_0.v
@@ -0,0 +1,332 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconcat_0_0,xlconcat_v2_1_4_xlconcat,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconcat_0_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
+DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,\
+IN62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_\
+WIDTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconcat_0_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml
new file mode 100644
index 0000000..6a0e5e8
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xml
@@ -0,0 +1,4808 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconcat_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>In0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
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+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 0)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN1_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN2_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 2)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN3_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 3)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In4</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN4_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 4)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In5</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN5_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 5)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In6</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN6_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 6)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In7</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN7_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 7)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In8</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN8_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 8)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In9</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN9_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In10</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN10_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 10)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In11</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN11_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 11)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In12</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN12_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 12)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In13</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN13_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.In13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.NUM_PORTS&apos;)) > 13)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>In14</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IN14_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.dout_width&apos;)) - 1)">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>IN0_WIDTH</spirit:name>
+        <spirit:displayName>In0 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN0_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN1_WIDTH</spirit:name>
+        <spirit:displayName>In1 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN1_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN2_WIDTH</spirit:name>
+        <spirit:displayName>In2 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN2_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN3_WIDTH</spirit:name>
+        <spirit:displayName>In3 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN3_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN4_WIDTH</spirit:name>
+        <spirit:displayName>In4 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN4_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN5_WIDTH</spirit:name>
+        <spirit:displayName>In5 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN5_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN6_WIDTH</spirit:name>
+        <spirit:displayName>In6 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN6_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN7_WIDTH</spirit:name>
+        <spirit:displayName>In7 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN7_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN8_WIDTH</spirit:name>
+        <spirit:displayName>In8 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN8_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN9_WIDTH</spirit:name>
+        <spirit:displayName>In9 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN9_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN10_WIDTH</spirit:name>
+        <spirit:displayName>In10 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN10_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN11_WIDTH</spirit:name>
+        <spirit:displayName>In11 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN11_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN12_WIDTH</spirit:name>
+        <spirit:displayName>In12 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN12_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN13_WIDTH</spirit:name>
+        <spirit:displayName>In13 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN13_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN14_WIDTH</spirit:name>
+        <spirit:displayName>In14 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN14_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN15_WIDTH</spirit:name>
+        <spirit:displayName>In15 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN15_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN16_WIDTH</spirit:name>
+        <spirit:displayName>In16 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN16_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN17_WIDTH</spirit:name>
+        <spirit:displayName>In17 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN17_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN18_WIDTH</spirit:name>
+        <spirit:displayName>In18 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN18_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN19_WIDTH</spirit:name>
+        <spirit:displayName>In19 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN19_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN20_WIDTH</spirit:name>
+        <spirit:displayName>In20 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN20_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN21_WIDTH</spirit:name>
+        <spirit:displayName>In21 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN21_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN22_WIDTH</spirit:name>
+        <spirit:displayName>In22 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN22_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN23_WIDTH</spirit:name>
+        <spirit:displayName>In23 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN23_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN24_WIDTH</spirit:name>
+        <spirit:displayName>In24 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN24_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN25_WIDTH</spirit:name>
+        <spirit:displayName>In25 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN25_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN26_WIDTH</spirit:name>
+        <spirit:displayName>In26 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN26_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN27_WIDTH</spirit:name>
+        <spirit:displayName>In27 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN27_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN28_WIDTH</spirit:name>
+        <spirit:displayName>In28 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN28_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN29_WIDTH</spirit:name>
+        <spirit:displayName>In29 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN29_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN30_WIDTH</spirit:name>
+        <spirit:displayName>In30 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN30_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN31_WIDTH</spirit:name>
+        <spirit:displayName>In31 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN31_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN32_WIDTH</spirit:name>
+        <spirit:displayName>In32 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN32_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN33_WIDTH</spirit:name>
+        <spirit:displayName>In33 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN33_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN34_WIDTH</spirit:name>
+        <spirit:displayName>In34 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN34_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN35_WIDTH</spirit:name>
+        <spirit:displayName>In35 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN35_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN36_WIDTH</spirit:name>
+        <spirit:displayName>In36 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN36_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN37_WIDTH</spirit:name>
+        <spirit:displayName>In37 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN37_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN38_WIDTH</spirit:name>
+        <spirit:displayName>In38 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN38_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN39_WIDTH</spirit:name>
+        <spirit:displayName>In39 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN39_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN40_WIDTH</spirit:name>
+        <spirit:displayName>In40 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN40_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN41_WIDTH</spirit:name>
+        <spirit:displayName>In41 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN41_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN42_WIDTH</spirit:name>
+        <spirit:displayName>In42 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN42_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN43_WIDTH</spirit:name>
+        <spirit:displayName>In43 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN43_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN44_WIDTH</spirit:name>
+        <spirit:displayName>In44 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN44_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN45_WIDTH</spirit:name>
+        <spirit:displayName>In45 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN45_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN46_WIDTH</spirit:name>
+        <spirit:displayName>In46 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN46_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN47_WIDTH</spirit:name>
+        <spirit:displayName>In47 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN47_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN48_WIDTH</spirit:name>
+        <spirit:displayName>In48 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN48_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN49_WIDTH</spirit:name>
+        <spirit:displayName>In49 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN49_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN50_WIDTH</spirit:name>
+        <spirit:displayName>In50 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN50_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN51_WIDTH</spirit:name>
+        <spirit:displayName>In51 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN51_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN52_WIDTH</spirit:name>
+        <spirit:displayName>In52 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN52_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN53_WIDTH</spirit:name>
+        <spirit:displayName>In53 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN53_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN54_WIDTH</spirit:name>
+        <spirit:displayName>In54 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN54_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN55_WIDTH</spirit:name>
+        <spirit:displayName>In55 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN55_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN56_WIDTH</spirit:name>
+        <spirit:displayName>In56 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN56_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN57_WIDTH</spirit:name>
+        <spirit:displayName>In57 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN57_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN58_WIDTH</spirit:name>
+        <spirit:displayName>In58 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN58_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN59_WIDTH</spirit:name>
+        <spirit:displayName>In59 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN59_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN60_WIDTH</spirit:name>
+        <spirit:displayName>In60 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN60_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN61_WIDTH</spirit:name>
+        <spirit:displayName>In61 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN61_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN62_WIDTH</spirit:name>
+        <spirit:displayName>In62 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN62_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN63_WIDTH</spirit:name>
+        <spirit:displayName>In63 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN63_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN64_WIDTH</spirit:name>
+        <spirit:displayName>In64 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN64_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN65_WIDTH</spirit:name>
+        <spirit:displayName>In65 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN65_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN66_WIDTH</spirit:name>
+        <spirit:displayName>In66 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN66_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN67_WIDTH</spirit:name>
+        <spirit:displayName>In67 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN67_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN68_WIDTH</spirit:name>
+        <spirit:displayName>In68 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN68_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN69_WIDTH</spirit:name>
+        <spirit:displayName>In69 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN69_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN70_WIDTH</spirit:name>
+        <spirit:displayName>In70 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN70_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN71_WIDTH</spirit:name>
+        <spirit:displayName>In71 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN71_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN72_WIDTH</spirit:name>
+        <spirit:displayName>In72 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN72_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN73_WIDTH</spirit:name>
+        <spirit:displayName>In73 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN73_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN74_WIDTH</spirit:name>
+        <spirit:displayName>In74 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN74_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN75_WIDTH</spirit:name>
+        <spirit:displayName>In75 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN75_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN76_WIDTH</spirit:name>
+        <spirit:displayName>In76 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN76_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN77_WIDTH</spirit:name>
+        <spirit:displayName>In77 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN77_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN78_WIDTH</spirit:name>
+        <spirit:displayName>In78 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN78_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN79_WIDTH</spirit:name>
+        <spirit:displayName>In79 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN79_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN80_WIDTH</spirit:name>
+        <spirit:displayName>In80 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN80_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN81_WIDTH</spirit:name>
+        <spirit:displayName>In81 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN81_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN82_WIDTH</spirit:name>
+        <spirit:displayName>In82 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN82_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN83_WIDTH</spirit:name>
+        <spirit:displayName>In83 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN83_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN84_WIDTH</spirit:name>
+        <spirit:displayName>In84 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN84_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN85_WIDTH</spirit:name>
+        <spirit:displayName>In85 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN85_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN86_WIDTH</spirit:name>
+        <spirit:displayName>In86 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN86_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN87_WIDTH</spirit:name>
+        <spirit:displayName>In87 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN87_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN88_WIDTH</spirit:name>
+        <spirit:displayName>In88 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN88_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN89_WIDTH</spirit:name>
+        <spirit:displayName>In89 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN89_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN90_WIDTH</spirit:name>
+        <spirit:displayName>In90 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN90_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN91_WIDTH</spirit:name>
+        <spirit:displayName>In91 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN91_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN92_WIDTH</spirit:name>
+        <spirit:displayName>In92 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN92_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN93_WIDTH</spirit:name>
+        <spirit:displayName>In93 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN93_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN94_WIDTH</spirit:name>
+        <spirit:displayName>In94 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN94_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN95_WIDTH</spirit:name>
+        <spirit:displayName>In95 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN95_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN96_WIDTH</spirit:name>
+        <spirit:displayName>In96 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN96_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN97_WIDTH</spirit:name>
+        <spirit:displayName>In97 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN97_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN98_WIDTH</spirit:name>
+        <spirit:displayName>In98 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN98_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN99_WIDTH</spirit:name>
+        <spirit:displayName>In99 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN99_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN100_WIDTH</spirit:name>
+        <spirit:displayName>In100 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN100_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN101_WIDTH</spirit:name>
+        <spirit:displayName>In101 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN101_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN102_WIDTH</spirit:name>
+        <spirit:displayName>In102 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN102_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN103_WIDTH</spirit:name>
+        <spirit:displayName>In103 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN103_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN104_WIDTH</spirit:name>
+        <spirit:displayName>In104 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN104_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN105_WIDTH</spirit:name>
+        <spirit:displayName>In105 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN105_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN106_WIDTH</spirit:name>
+        <spirit:displayName>In106 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN106_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN107_WIDTH</spirit:name>
+        <spirit:displayName>In107 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN107_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN108_WIDTH</spirit:name>
+        <spirit:displayName>In108 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN108_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN109_WIDTH</spirit:name>
+        <spirit:displayName>In109 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN109_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN110_WIDTH</spirit:name>
+        <spirit:displayName>In110 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN110_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN111_WIDTH</spirit:name>
+        <spirit:displayName>In111 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN111_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN112_WIDTH</spirit:name>
+        <spirit:displayName>In112 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN112_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN113_WIDTH</spirit:name>
+        <spirit:displayName>In113 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN113_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN114_WIDTH</spirit:name>
+        <spirit:displayName>In114 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN114_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN115_WIDTH</spirit:name>
+        <spirit:displayName>In115 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN115_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN116_WIDTH</spirit:name>
+        <spirit:displayName>In116 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN116_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN117_WIDTH</spirit:name>
+        <spirit:displayName>In117 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN117_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN118_WIDTH</spirit:name>
+        <spirit:displayName>In118 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN118_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN119_WIDTH</spirit:name>
+        <spirit:displayName>In119 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN119_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN120_WIDTH</spirit:name>
+        <spirit:displayName>In120 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN120_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN121_WIDTH</spirit:name>
+        <spirit:displayName>In121 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN121_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN122_WIDTH</spirit:name>
+        <spirit:displayName>In122 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN122_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN123_WIDTH</spirit:name>
+        <spirit:displayName>In123 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN123_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN124_WIDTH</spirit:name>
+        <spirit:displayName>In124 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN124_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN125_WIDTH</spirit:name>
+        <spirit:displayName>In125 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN125_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN126_WIDTH</spirit:name>
+        <spirit:displayName>In126 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN126_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IN127_WIDTH</spirit:name>
+        <spirit:displayName>In127 Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IN127_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>dout_width</spirit:name>
+        <spirit:displayName>Dout Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.dout_width">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_PORTS</spirit:name>
+        <spirit:displayName>Number of Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PORTS">2</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Concatenates up to 128 ports into a single port</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconcat_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>NUM_PORTS</spirit:name>
+      <spirit:displayName>Number of Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PORTS" spirit:order="3" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN0_WIDTH</spirit:name>
+      <spirit:displayName>In0 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN0_WIDTH" spirit:order="4" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN1_WIDTH</spirit:name>
+      <spirit:displayName>In1 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN1_WIDTH" spirit:order="5" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN2_WIDTH</spirit:name>
+      <spirit:displayName>In2 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN2_WIDTH" spirit:order="6" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN3_WIDTH</spirit:name>
+      <spirit:displayName>In3 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN3_WIDTH" spirit:order="7" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN4_WIDTH</spirit:name>
+      <spirit:displayName>In4 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN4_WIDTH" spirit:order="8" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN5_WIDTH</spirit:name>
+      <spirit:displayName>In5 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN5_WIDTH" spirit:order="9" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN6_WIDTH</spirit:name>
+      <spirit:displayName>In6 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN6_WIDTH" spirit:order="10" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN7_WIDTH</spirit:name>
+      <spirit:displayName>In7 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN7_WIDTH" spirit:order="11" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN8_WIDTH</spirit:name>
+      <spirit:displayName>In8 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN8_WIDTH" spirit:order="12" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN9_WIDTH</spirit:name>
+      <spirit:displayName>In9 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN9_WIDTH" spirit:order="13" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN10_WIDTH</spirit:name>
+      <spirit:displayName>In10 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN10_WIDTH" spirit:order="14" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN11_WIDTH</spirit:name>
+      <spirit:displayName>In11 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN11_WIDTH" spirit:order="15" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN12_WIDTH</spirit:name>
+      <spirit:displayName>In12 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN12_WIDTH" spirit:order="16" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN13_WIDTH</spirit:name>
+      <spirit:displayName>In13 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN13_WIDTH" spirit:order="17" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN14_WIDTH</spirit:name>
+      <spirit:displayName>In14 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN14_WIDTH" spirit:order="18" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN15_WIDTH</spirit:name>
+      <spirit:displayName>In15 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN15_WIDTH" spirit:order="19" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN16_WIDTH</spirit:name>
+      <spirit:displayName>In16 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN16_WIDTH" spirit:order="20" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN17_WIDTH</spirit:name>
+      <spirit:displayName>In17 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN17_WIDTH" spirit:order="21" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN18_WIDTH</spirit:name>
+      <spirit:displayName>In18 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN18_WIDTH" spirit:order="22" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN19_WIDTH</spirit:name>
+      <spirit:displayName>In19 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN19_WIDTH" spirit:order="23" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN20_WIDTH</spirit:name>
+      <spirit:displayName>In20 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN20_WIDTH" spirit:order="24" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN21_WIDTH</spirit:name>
+      <spirit:displayName>In21 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN21_WIDTH" spirit:order="25" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN22_WIDTH</spirit:name>
+      <spirit:displayName>In22 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN22_WIDTH" spirit:order="26" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN23_WIDTH</spirit:name>
+      <spirit:displayName>In23 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN23_WIDTH" spirit:order="27" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN24_WIDTH</spirit:name>
+      <spirit:displayName>In24 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN24_WIDTH" spirit:order="28" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN25_WIDTH</spirit:name>
+      <spirit:displayName>In25 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN25_WIDTH" spirit:order="29" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN26_WIDTH</spirit:name>
+      <spirit:displayName>In26 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN26_WIDTH" spirit:order="30" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN27_WIDTH</spirit:name>
+      <spirit:displayName>In27 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN27_WIDTH" spirit:order="31" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN28_WIDTH</spirit:name>
+      <spirit:displayName>In28 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN28_WIDTH" spirit:order="32" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN29_WIDTH</spirit:name>
+      <spirit:displayName>In29 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN29_WIDTH" spirit:order="33" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN30_WIDTH</spirit:name>
+      <spirit:displayName>In30 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN30_WIDTH" spirit:order="34" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN31_WIDTH</spirit:name>
+      <spirit:displayName>In31 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN31_WIDTH" spirit:order="35" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN32_WIDTH</spirit:name>
+      <spirit:displayName>In32 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN32_WIDTH" spirit:order="36" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN33_WIDTH</spirit:name>
+      <spirit:displayName>In33 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN33_WIDTH" spirit:order="37" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN34_WIDTH</spirit:name>
+      <spirit:displayName>In34 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN34_WIDTH" spirit:order="38" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN35_WIDTH</spirit:name>
+      <spirit:displayName>In35 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN35_WIDTH" spirit:order="39" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN36_WIDTH</spirit:name>
+      <spirit:displayName>In36 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN36_WIDTH" spirit:order="40" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN37_WIDTH</spirit:name>
+      <spirit:displayName>In37 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN37_WIDTH" spirit:order="41" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN38_WIDTH</spirit:name>
+      <spirit:displayName>In38 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN38_WIDTH" spirit:order="42" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN39_WIDTH</spirit:name>
+      <spirit:displayName>In39 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN39_WIDTH" spirit:order="43" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN40_WIDTH</spirit:name>
+      <spirit:displayName>In40 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN40_WIDTH" spirit:order="44" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN41_WIDTH</spirit:name>
+      <spirit:displayName>In41 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN41_WIDTH" spirit:order="45" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN42_WIDTH</spirit:name>
+      <spirit:displayName>In42 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN42_WIDTH" spirit:order="46" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN43_WIDTH</spirit:name>
+      <spirit:displayName>In43 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN43_WIDTH" spirit:order="47" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN44_WIDTH</spirit:name>
+      <spirit:displayName>In44 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN44_WIDTH" spirit:order="48" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN45_WIDTH</spirit:name>
+      <spirit:displayName>In45 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN45_WIDTH" spirit:order="49" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN46_WIDTH</spirit:name>
+      <spirit:displayName>In46 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN46_WIDTH" spirit:order="50" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN47_WIDTH</spirit:name>
+      <spirit:displayName>In47 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN47_WIDTH" spirit:order="51" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN48_WIDTH</spirit:name>
+      <spirit:displayName>In48 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN48_WIDTH" spirit:order="52" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN49_WIDTH</spirit:name>
+      <spirit:displayName>In49 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN49_WIDTH" spirit:order="53" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN50_WIDTH</spirit:name>
+      <spirit:displayName>In50 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN50_WIDTH" spirit:order="54" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN51_WIDTH</spirit:name>
+      <spirit:displayName>In51 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN51_WIDTH" spirit:order="55" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN52_WIDTH</spirit:name>
+      <spirit:displayName>In52 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN52_WIDTH" spirit:order="56" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN53_WIDTH</spirit:name>
+      <spirit:displayName>In53 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN53_WIDTH" spirit:order="57" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN54_WIDTH</spirit:name>
+      <spirit:displayName>In54 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN54_WIDTH" spirit:order="58" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN55_WIDTH</spirit:name>
+      <spirit:displayName>In55 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN55_WIDTH" spirit:order="60" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN56_WIDTH</spirit:name>
+      <spirit:displayName>In56 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN56_WIDTH" spirit:order="61" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN57_WIDTH</spirit:name>
+      <spirit:displayName>In57 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN57_WIDTH" spirit:order="62" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN58_WIDTH</spirit:name>
+      <spirit:displayName>In58 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN58_WIDTH" spirit:order="63" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN59_WIDTH</spirit:name>
+      <spirit:displayName>In59 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN59_WIDTH" spirit:order="64" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN60_WIDTH</spirit:name>
+      <spirit:displayName>In60 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN60_WIDTH" spirit:order="65" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN61_WIDTH</spirit:name>
+      <spirit:displayName>In61 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN61_WIDTH" spirit:order="66" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN62_WIDTH</spirit:name>
+      <spirit:displayName>In62 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN62_WIDTH" spirit:order="67" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN63_WIDTH</spirit:name>
+      <spirit:displayName>In63 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN63_WIDTH" spirit:order="68" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN64_WIDTH</spirit:name>
+      <spirit:displayName>In64 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN64_WIDTH" spirit:order="69" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN65_WIDTH</spirit:name>
+      <spirit:displayName>In65 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN65_WIDTH" spirit:order="70" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN66_WIDTH</spirit:name>
+      <spirit:displayName>In66 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN66_WIDTH" spirit:order="71" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN67_WIDTH</spirit:name>
+      <spirit:displayName>In67 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN67_WIDTH" spirit:order="72" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN68_WIDTH</spirit:name>
+      <spirit:displayName>In68 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN68_WIDTH" spirit:order="73" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN69_WIDTH</spirit:name>
+      <spirit:displayName>In69 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN69_WIDTH" spirit:order="74" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN70_WIDTH</spirit:name>
+      <spirit:displayName>In70 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN70_WIDTH" spirit:order="75" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN71_WIDTH</spirit:name>
+      <spirit:displayName>In71 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN71_WIDTH" spirit:order="76" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN72_WIDTH</spirit:name>
+      <spirit:displayName>In72 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN72_WIDTH" spirit:order="77" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN73_WIDTH</spirit:name>
+      <spirit:displayName>In73 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN73_WIDTH" spirit:order="78" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN74_WIDTH</spirit:name>
+      <spirit:displayName>In74 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN74_WIDTH" spirit:order="79" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN75_WIDTH</spirit:name>
+      <spirit:displayName>In75 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN75_WIDTH" spirit:order="80" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN76_WIDTH</spirit:name>
+      <spirit:displayName>In76 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN76_WIDTH" spirit:order="81" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN77_WIDTH</spirit:name>
+      <spirit:displayName>In77 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN77_WIDTH" spirit:order="83" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN78_WIDTH</spirit:name>
+      <spirit:displayName>In78 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN78_WIDTH" spirit:order="84" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN79_WIDTH</spirit:name>
+      <spirit:displayName>In79 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN79_WIDTH" spirit:order="85" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN80_WIDTH</spirit:name>
+      <spirit:displayName>In80 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN80_WIDTH" spirit:order="86" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN81_WIDTH</spirit:name>
+      <spirit:displayName>In81 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN81_WIDTH" spirit:order="87" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN82_WIDTH</spirit:name>
+      <spirit:displayName>In82 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN82_WIDTH" spirit:order="88" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN83_WIDTH</spirit:name>
+      <spirit:displayName>In83 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN83_WIDTH" spirit:order="89" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN84_WIDTH</spirit:name>
+      <spirit:displayName>In84 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN84_WIDTH" spirit:order="90" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN85_WIDTH</spirit:name>
+      <spirit:displayName>In85 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN85_WIDTH" spirit:order="91" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN86_WIDTH</spirit:name>
+      <spirit:displayName>In86 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN86_WIDTH" spirit:order="92" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN87_WIDTH</spirit:name>
+      <spirit:displayName>In87 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN87_WIDTH" spirit:order="93" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN88_WIDTH</spirit:name>
+      <spirit:displayName>In88 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN88_WIDTH" spirit:order="94" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN89_WIDTH</spirit:name>
+      <spirit:displayName>In89 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN89_WIDTH" spirit:order="95" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN90_WIDTH</spirit:name>
+      <spirit:displayName>In90 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN90_WIDTH" spirit:order="96" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN91_WIDTH</spirit:name>
+      <spirit:displayName>In91 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN91_WIDTH" spirit:order="97" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN92_WIDTH</spirit:name>
+      <spirit:displayName>In92 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN92_WIDTH" spirit:order="98" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN93_WIDTH</spirit:name>
+      <spirit:displayName>In93 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN93_WIDTH" spirit:order="99" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN94_WIDTH</spirit:name>
+      <spirit:displayName>In94 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN94_WIDTH" spirit:order="100" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN95_WIDTH</spirit:name>
+      <spirit:displayName>In95 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN95_WIDTH" spirit:order="101" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN96_WIDTH</spirit:name>
+      <spirit:displayName>In96 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN96_WIDTH" spirit:order="102" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN97_WIDTH</spirit:name>
+      <spirit:displayName>In97 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN97_WIDTH" spirit:order="103" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN98_WIDTH</spirit:name>
+      <spirit:displayName>In98 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN98_WIDTH" spirit:order="104" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN99_WIDTH</spirit:name>
+      <spirit:displayName>In99 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN99_WIDTH" spirit:order="105" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN100_WIDTH</spirit:name>
+      <spirit:displayName>In100 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN100_WIDTH" spirit:order="106" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN101_WIDTH</spirit:name>
+      <spirit:displayName>In101 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN101_WIDTH" spirit:order="107" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN102_WIDTH</spirit:name>
+      <spirit:displayName>In102 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN102_WIDTH" spirit:order="108" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN103_WIDTH</spirit:name>
+      <spirit:displayName>In103 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN103_WIDTH" spirit:order="109" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN104_WIDTH</spirit:name>
+      <spirit:displayName>In104 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN104_WIDTH" spirit:order="110" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN105_WIDTH</spirit:name>
+      <spirit:displayName>In105 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN105_WIDTH" spirit:order="111" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN106_WIDTH</spirit:name>
+      <spirit:displayName>In106 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN106_WIDTH" spirit:order="112" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN107_WIDTH</spirit:name>
+      <spirit:displayName>In107 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN107_WIDTH" spirit:order="113" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN108_WIDTH</spirit:name>
+      <spirit:displayName>In108 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN108_WIDTH" spirit:order="114" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN109_WIDTH</spirit:name>
+      <spirit:displayName>In109 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN109_WIDTH" spirit:order="115" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN110_WIDTH</spirit:name>
+      <spirit:displayName>In110 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN110_WIDTH" spirit:order="116" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN111_WIDTH</spirit:name>
+      <spirit:displayName>In111 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN111_WIDTH" spirit:order="117" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN112_WIDTH</spirit:name>
+      <spirit:displayName>In112 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN112_WIDTH" spirit:order="118" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN113_WIDTH</spirit:name>
+      <spirit:displayName>In113 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN113_WIDTH" spirit:order="119" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN114_WIDTH</spirit:name>
+      <spirit:displayName>In114 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN114_WIDTH" spirit:order="120" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN115_WIDTH</spirit:name>
+      <spirit:displayName>In115 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN115_WIDTH" spirit:order="121" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN116_WIDTH</spirit:name>
+      <spirit:displayName>In116 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN116_WIDTH" spirit:order="122" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN117_WIDTH</spirit:name>
+      <spirit:displayName>In117 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN117_WIDTH" spirit:order="123" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN118_WIDTH</spirit:name>
+      <spirit:displayName>In118 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN118_WIDTH" spirit:order="124" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN119_WIDTH</spirit:name>
+      <spirit:displayName>In119 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN119_WIDTH" spirit:order="125" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN120_WIDTH</spirit:name>
+      <spirit:displayName>In120 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN120_WIDTH" spirit:order="126" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN121_WIDTH</spirit:name>
+      <spirit:displayName>In121 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN121_WIDTH" spirit:order="127" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN122_WIDTH</spirit:name>
+      <spirit:displayName>In122 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN122_WIDTH" spirit:order="128" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN123_WIDTH</spirit:name>
+      <spirit:displayName>In123 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN123_WIDTH" spirit:order="129" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN124_WIDTH</spirit:name>
+      <spirit:displayName>In124 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN124_WIDTH" spirit:order="130" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN125_WIDTH</spirit:name>
+      <spirit:displayName>In125 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN125_WIDTH" spirit:order="131" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN126_WIDTH</spirit:name>
+      <spirit:displayName>In126 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN126_WIDTH" spirit:order="132" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN127_WIDTH</spirit:name>
+      <spirit:displayName>In127 Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IN127_WIDTH" spirit:order="133" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dout_width</spirit:name>
+      <spirit:displayName>Dout Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.dout_width" spirit:order="134">2</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Concat</xilinx:displayName>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN0_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN100_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN101_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN102_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN103_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN104_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN105_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN106_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN107_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN108_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN109_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN10_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN110_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN111_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN112_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN113_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN114_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN115_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN116_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN117_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN118_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN119_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN11_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN120_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN121_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN122_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN123_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN124_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN125_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN126_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN127_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN12_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN13_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN14_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN15_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN16_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN17_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN18_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN19_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN1_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN20_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN21_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN22_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN23_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN24_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN25_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN26_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN27_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN28_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN29_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN2_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN30_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN31_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN32_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN33_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN34_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN35_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN36_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN37_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN38_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN39_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN3_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN40_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN41_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN42_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN43_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN44_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN45_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN46_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN47_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN48_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN49_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN4_WIDTH" xilinx:valuePermission="bd_and_user"/>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xml
new file mode 100644
index 0000000..b8405ca
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xml
@@ -0,0 +1,274 @@
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
new file mode 100644
index 0000000..a112873
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [7 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(8),
+    .CONST_VAL(8'H00)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv
new file mode 100644
index 0000000..69b0562
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0_stub.sv
@@ -0,0 +1,86 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+//------------------------------------------------------------------------------------
+// Filename:    xl_Constant_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`ifdef XILINX_SIMULATOR
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_0 (
+  output bit [7 : 0 ] dout
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_xlconstant_0_0 (dout)
+(* integer foreign = "SystemC";
+*);
+ output wire [7 : 0 ] dout;  
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_0 (dout)
+  output wire [7 : 0 ] dout;
+endmodule
+`endif
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v
new file mode 100644
index 0000000..239a973
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/synth/design_1_xlconstant_0_0.v
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=8,CONST_VAL=0x00}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [7 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(8),
+    .CONST_VAL(8'H00)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml
new file mode 100644
index 0000000..82838a6
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconstant_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>CONST_WIDTH</spirit:name>
+        <spirit:displayName>Const Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CONST_VAL</spirit:name>
+        <spirit:displayName>Const Val</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconstant_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml
new file mode 100644
index 0000000..cc7dfd5
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconstant_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
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+      <spirit:view>
+        <spirit:name>xilinx_systemcsimulation</spirit:name>
+        <spirit:displayName>SystemC Simulation</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>xlconstant_v1_1_7</spirit:modelName>
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+            <spirit:value>tlm</spirit:value>
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+        <spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>design_1_xlconstant_0_1</spirit:modelName>
+        <spirit:fileSetRef>
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+    <spirit:ports>
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+        <spirit:name>dout</spirit:name>
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+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
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diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
new file mode 100644
index 0000000..31c4f41
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_1 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv
new file mode 100644
index 0000000..1ececcc
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1_stub.sv
@@ -0,0 +1,86 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+//------------------------------------------------------------------------------------
+// Filename:    xl_Constant_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`ifdef XILINX_SIMULATOR
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_1 (
+  output bit [0 : 0 ] dout
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_xlconstant_0_1 (dout)
+(* integer foreign = "SystemC";
+*);
+ output wire [0 : 0 ] dout;  
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_1 (dout)
+  output wire [0 : 0 ] dout;
+endmodule
+`endif
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/sim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v
new file mode 100644
index 0000000..5b9fbaa
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/synth/design_1_xlconstant_0_1.v
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_1 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml
new file mode 100644
index 0000000..cf4bf5b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconstant_0_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>CONST_WIDTH</spirit:name>
+        <spirit:displayName>Const Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CONST_VAL</spirit:name>
+        <spirit:displayName>Const Val</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconstant_0_1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml
new file mode 100644
index 0000000..74b403f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconstant_0_2</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+        <spirit:displayName>Verilog Simulation</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e4c63470</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_systemcsimulation</spirit:name>
+        <spirit:displayName>SystemC Simulation</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>xlconstant_v1_1_7</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:48:36 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e4c63470</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>sim_type</spirit:name>
+            <spirit:value>tlm</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
+        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_xlconstant_0_2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:48:36 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e4c63470</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
+        <spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>design_1_xlconstant_0_2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:48:37 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e4c63470</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>sim_type</spirit:name>
+            <spirit:value>tlm</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:58845e65</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:58845e65</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_xlconstant_0_2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:07 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:58845e65</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>CONST_WIDTH</spirit:name>
+        <spirit:displayName>Const Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CONST_VAL</spirit:name>
+        <spirit:displayName>Const Val</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/xlconstant_v1_1_7.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_2.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_2.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_2.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlconstant_0_2_stub.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_xlconstant_0_2.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconstant_0_2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
new file mode 100644
index 0000000..5011eda
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_2 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv
new file mode 100644
index 0000000..769cc9b
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2_stub.sv
@@ -0,0 +1,86 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+//------------------------------------------------------------------------------------
+// Filename:    xl_Constant_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`ifdef XILINX_SIMULATOR
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_2 (
+  output bit [0 : 0 ] dout
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_xlconstant_0_2 (dout)
+(* integer foreign = "SystemC";
+*);
+ output wire [0 : 0 ] dout;  
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_2 (dout)
+  output wire [0 : 0 ] dout;
+endmodule
+`endif
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/sim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v
new file mode 100644
index 0000000..92f6a90
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/synth/design_1_xlconstant_0_2.v
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_2,xlconstant_v1_1_7_xlconstant,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconstant_0_2,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_2 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml
new file mode 100644
index 0000000..4e061df
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xml
@@ -0,0 +1,273 @@
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+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
new file mode 100644
index 0000000..65ddfe3
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_3 (
+  dout
+);
+
+output wire [23 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(24),
+    .CONST_VAL(24'H000001)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv
new file mode 100644
index 0000000..931a227
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3_stub.sv
@@ -0,0 +1,86 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+//------------------------------------------------------------------------------------
+// Filename:    xl_Constant_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`ifdef XILINX_SIMULATOR
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_3 (
+  output bit [23 : 0 ] dout
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module design_1_xlconstant_0_3 (dout)
+(* integer foreign = "SystemC";
+*);
+ output wire [23 : 0 ] dout;  
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module design_1_xlconstant_0_3 (dout)
+  output wire [23 : 0 ] dout;
+endmodule
+`endif
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/sim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v
new file mode 100644
index 0000000..796ce2a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/synth/design_1_xlconstant_0_3.v
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_3,xlconstant_v1_1_7_xlconstant,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlconstant_0_3,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=24,CONST_VAL=0x000001}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_3 (
+  dout
+);
+
+output wire [23 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(24),
+    .CONST_VAL(24'H000001)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml
new file mode 100644
index 0000000..b939c0f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xml
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlconstant_1_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>CONST_WIDTH</spirit:name>
+        <spirit:displayName>Const Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">24</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CONST_VAL</spirit:name>
+        <spirit:displayName>Const Val</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="24">0x000001</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Gives a constant signed value.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlconstant_1_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_WIDTH</spirit:name>
+      <spirit:displayName>Const Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CONST_VAL</spirit:name>
+      <spirit:displayName>Const Val</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Constant</xilinx:displayName>
+      <xilinx:coreRevision>7</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml
new file mode 100644
index 0000000..ce87e59
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlslice_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+        <spirit:displayName>Verilog Simulation</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>xlslice_v1_0_2_xlslice</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2b317e54</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
+        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_xlslice_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:2b317e54</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>xlslice_v1_0_2_xlslice</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Apr 18 16:39:42 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:c6ad224f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:c6ad224f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>design_1_xlslice_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Tue Jan 16 16:56:06 UTC 2024</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:c6ad224f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Din</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_WIDTH&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_FROM&apos;)) - spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_TO&apos;)))">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>DIN_WIDTH</spirit:name>
+        <spirit:displayName>Din Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_WIDTH">24</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DIN_FROM</spirit:name>
+        <spirit:displayName>Din From</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_FROM">23</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DIN_TO</spirit:name>
+        <spirit:displayName>Din Down To</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_TO">23</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>xlslice_v1_0_2</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/design_1_xlslice_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xlslice_v1_0_2</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/design_1_xlslice_0_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>Slices a number of bits off of Din input. dout = din[from_position : to_position]</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlslice_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_TO</spirit:name>
+      <spirit:displayName>Din Down To</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_TO" spirit:order="3" spirit:minimum="0" spirit:maximum="23" spirit:rangeType="long">23</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_FROM</spirit:name>
+      <spirit:displayName>Din From</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_FROM" spirit:order="4" spirit:minimum="23" spirit:maximum="23" spirit:rangeType="long">23</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_WIDTH</spirit:name>
+      <spirit:displayName>Din Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_WIDTH" spirit:order="5" spirit:minimum="2" spirit:maximum="4096" spirit:rangeType="long">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DOUT_WIDTH</spirit:name>
+      <spirit:displayName>Dout Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_WIDTH" spirit:order="6">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Slice</xilinx:displayName>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_FROM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_TO" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DOUT_WIDTH" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="919195e7"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="5abcbb1c"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="50a9af96"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="37b3740b"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
new file mode 100644
index 0000000..c5f22b1
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
@@ -0,0 +1,72 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlslice:1.0
+// IP Revision: 2
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlslice_0_0 (
+  Din,
+  Dout
+);
+
+input wire [23 : 0] Din;
+output wire [0 : 0] Dout;
+
+  xlslice_v1_0_2_xlslice #(
+    .DIN_WIDTH(24),
+    .DIN_FROM(23),
+    .DIN_TO(23)
+  ) inst (
+    .Din(Din),
+    .Dout(Dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v
new file mode 100644
index 0000000..a9d492d
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.v
@@ -0,0 +1,73 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlslice:1.0
+// IP Revision: 2
+
+(* X_CORE_INFO = "xlslice_v1_0_2_xlslice,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "design_1_xlslice_0_0,xlslice_v1_0_2_xlslice,{}" *)
+(* CORE_GENERATION_INFO = "design_1_xlslice_0_0,xlslice_v1_0_2_xlslice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=24,DIN_FROM=23,DIN_TO=23}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlslice_0_0 (
+  Din,
+  Dout
+);
+
+input wire [23 : 0] Din;
+output wire [0 : 0] Dout;
+
+  xlslice_v1_0_2_xlslice #(
+    .DIN_WIDTH(24),
+    .DIN_FROM(23),
+    .DIN_TO(23)
+  ) inst (
+    .Din(Din),
+    .Dout(Dout)
+  );
+endmodule
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml
new file mode 100644
index 0000000..ff6931d
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>design_1_xlslice_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Din</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_WIDTH&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Dout</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_FROM&apos;)) - spirit:decode(id(&apos;MODELPARAM_VALUE.DIN_TO&apos;)))">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>DIN_WIDTH</spirit:name>
+        <spirit:displayName>Din Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_WIDTH">24</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DIN_FROM</spirit:name>
+        <spirit:displayName>Din From</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_FROM">23</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DIN_TO</spirit:name>
+        <spirit:displayName>Din Down To</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIN_TO">23</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:description>Slices a number of bits off of Din input. dout = din[from_position : to_position]</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">design_1_xlslice_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_TO</spirit:name>
+      <spirit:displayName>Din Down To</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_TO" spirit:order="3" spirit:minimum="0" spirit:maximum="23" spirit:rangeType="long">23</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_FROM</spirit:name>
+      <spirit:displayName>Din From</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_FROM" spirit:order="4" spirit:minimum="23" spirit:maximum="23" spirit:rangeType="long">23</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_WIDTH</spirit:name>
+      <spirit:displayName>Din Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_WIDTH" spirit:order="5" spirit:minimum="2" spirit:maximum="4096" spirit:rangeType="long">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DOUT_WIDTH</spirit:name>
+      <spirit:displayName>Dout Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_WIDTH" spirit:order="6">1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Slice</xilinx:displayName>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_FROM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_TO" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DOUT_WIDTH" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="919195e7"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="5abcbb1c"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="50a9af96"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="37b3740b"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v
new file mode 100644
index 0000000..0a10ec3
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v
@@ -0,0 +1,25 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlslice.v
+//--
+//--  Date          : 06/05/12
+//-
+//-  Description   : Verilog description of a slice block.  This
+//-                  block does not use a core.
+//-
+//-----------------------------------------------------------------------
+
+`timescale 1ps/1ps
+module  xlslice_v1_0_2_xlslice (Din,Dout);
+
+	parameter DIN_WIDTH  = 32;
+	parameter DIN_FROM = 8;
+	parameter DIN_TO = 8;
+	
+	input [DIN_WIDTH -1:0] Din;
+	output [DIN_FROM - DIN_TO:0] Dout;
+	 
+	assign Dout = Din [DIN_FROM: DIN_TO];
+endmodule
+
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v
new file mode 100644
index 0000000..9c42c12
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v
@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+/*
+-------------------------------------------------------------------------------
+-- $Id: util_vector_logic.v 2.0 2017/01/01 
+-------------------------------------------------------------------------------
+--
+--  ***************************************************************************
+--  **  Copyright(C) 2017 by Xilinx, Inc. All rights reserved.               **
+--  **                                                                       **
+--  **  This text contains proprietary, confidential                         **
+--  **  information of Xilinx, Inc. , is distributed by                      **
+--  **  under license from Xilinx, Inc., and may be used,                    **
+--  **  copied and/or disclosed only pursuant to the terms                   **
+--  **  of a valid license agreement with Xilinx, Inc.                       **
+--  **                                                                       **
+--  **  Unmodified source code is guaranteed to place and route,             **
+--  **  function and run at speed according to the datasheet                 **
+--  **  specification. Source code is provided "as-is", with no              **
+--  **  obligation on the part of Xilinx to provide support.                 **
+--  **                                                                       **
+--  **  Xilinx Hotline support of source code IP shall only include          **
+--  **  standard level Xilinx Hotline support, and will only address         **
+--  **  issues and questions related to the standard released Netlist        **
+--  **  version of the core (and thus indirectly, the original core source). **
+--  **                                                                       **
+--  **  The Xilinx Support Hotline does not have access to source            **
+--  **  code and therefore cannot answer specific questions related          **
+--  **  to source HDL. The Xilinx Support Hotline will only be able          **
+--  **  to confirm the problem in the Netlist version of the core.           **
+--  **                                                                       **
+--  **  This copyright and support notice must be retained as part           **
+--  **  of this text at all times.                                           **
+--  ***************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        util_vector_logic.v
+--
+-- Description: 
+--                  
+-- Verilog-Standard:
+-------------------------------------------------------------------------------
+*/
+
+
+module util_vector_logic_v2_0_1_util_vector_logic ( Op1, Op2, Res);
+ 
+parameter         C_OPERATION = "and";
+parameter integer C_SIZE = 8;
+
+input  [C_SIZE - 1:0] Op1; 
+input  [C_SIZE - 1:0] Op2; 
+output [C_SIZE - 1:0] Res; 
+
+//wire   [C_SIZE - 1:0] Res; 
+//parameter C_Oper = C_OPERATION; 
+
+generate if (C_OPERATION == "and") begin: GEN_AND_OP
+    assign Res = Op1 & Op2; 
+end
+endgenerate
+
+generate if (C_OPERATION == "or")  begin: GEN_OR_OP
+   assign Res = Op1 | Op2; 
+end
+endgenerate
+
+generate if (C_OPERATION == "xor") begin: GEN_XOR_OP
+    assign Res = Op1 ^ Op2; 
+end
+endgenerate
+
+generate if (C_OPERATION == "not") begin: GEN_NOT_OP
+    assign Res = ~Op1; 
+end
+endgenerate
+
+endmodule // module util_vector_logic
+
+
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v
new file mode 100644
index 0000000..f92a18e
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v
@@ -0,0 +1,1041 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlconcat.v
+//--
+//--  Date          : 06/05/12
+//-
+//-  Description   : Verilog description of a concat block.  This
+//-                  block does not use a core.
+//-
+//-----------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module xlconcat_v2_1_4_xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31,In32, In33, In34, In35, In36, In37, In38, In39, In40, In41,In42, In43, In44, In45, In46, In47, In48, In49,In50, In51,In52, In53, In54, In55, In56, In57, In58, In59,In60, In61,In62, In63, In64, In65, In66, In67, In68, In69,In70, In71,In72, In73, In74, In75, In76, In77, In78, In79, In80, In81,In82, In83, In84, In85, In86, In87, In88, In89,In90, In91,In92, In93, In94, In95, In96, In97, In98, In99,In100, In101,In102, In103, In104, In105, In106, In107, In108, In109,In110, In111,In112, In113, In114, In115, In116, In117, In118, In119,In120, In121,In122, In123, In124, In125, In126, In127,dout);
+parameter IN0_WIDTH = 1;
+input 	[IN0_WIDTH -1:0] In0;
+parameter IN1_WIDTH = 1;
+input 	[IN1_WIDTH -1:0] In1;
+parameter IN2_WIDTH = 1;
+input 	[IN2_WIDTH -1:0] In2;
+parameter IN3_WIDTH = 1;
+input 	[IN3_WIDTH -1:0] In3;
+parameter IN4_WIDTH = 1;
+input 	[IN4_WIDTH -1:0] In4;
+parameter IN5_WIDTH = 1;
+input 	[IN5_WIDTH -1:0] In5;
+parameter IN6_WIDTH = 1;
+input 	[IN6_WIDTH -1:0] In6;
+parameter IN7_WIDTH = 1;
+input 	[IN7_WIDTH -1:0] In7;
+parameter IN8_WIDTH = 1;
+input 	[IN8_WIDTH -1:0] In8;
+parameter IN9_WIDTH = 1;
+input 	[IN9_WIDTH -1:0] In9;
+parameter IN10_WIDTH = 1;
+input 	[IN10_WIDTH -1:0] In10;
+parameter IN11_WIDTH = 1;
+input 	[IN11_WIDTH -1:0] In11;
+parameter IN12_WIDTH = 1;
+input 	[IN12_WIDTH -1:0] In12;
+parameter IN13_WIDTH = 1;
+input 	[IN13_WIDTH -1:0] In13;
+parameter IN14_WIDTH = 1;
+input 	[IN14_WIDTH -1:0] In14;
+parameter IN15_WIDTH = 1;
+input 	[IN15_WIDTH -1:0] In15;
+parameter IN16_WIDTH = 1;
+input 	[IN16_WIDTH -1:0] In16;
+parameter IN17_WIDTH = 1;
+input 	[IN17_WIDTH -1:0] In17;
+parameter IN18_WIDTH = 1;
+input 	[IN18_WIDTH -1:0] In18;
+parameter IN19_WIDTH = 1;
+input 	[IN19_WIDTH -1:0] In19;
+parameter IN20_WIDTH = 1;
+input 	[IN20_WIDTH -1:0] In20;
+parameter IN21_WIDTH = 1;
+input 	[IN21_WIDTH -1:0] In21;
+parameter IN22_WIDTH = 1;
+input 	[IN22_WIDTH -1:0] In22;
+parameter IN23_WIDTH = 1;
+input 	[IN23_WIDTH -1:0] In23;
+parameter IN24_WIDTH = 1;
+input 	[IN24_WIDTH -1:0] In24;
+parameter IN25_WIDTH = 1;
+input 	[IN25_WIDTH -1:0] In25;
+parameter IN26_WIDTH = 1;
+input 	[IN26_WIDTH -1:0] In26;
+parameter IN27_WIDTH = 1;
+input 	[IN27_WIDTH -1:0] In27;
+parameter IN28_WIDTH = 1;
+input 	[IN28_WIDTH -1:0] In28;
+parameter IN29_WIDTH = 1;
+input 	[IN29_WIDTH -1:0] In29;
+parameter IN30_WIDTH = 1;
+input 	[IN30_WIDTH -1:0] In30;
+parameter IN31_WIDTH = 1;
+input 	[IN31_WIDTH -1:0] In31;
+parameter IN32_WIDTH = 1;
+input 	[IN32_WIDTH -1:0] In32;
+parameter IN33_WIDTH = 1;
+input 	[IN33_WIDTH -1:0] In33;
+parameter IN34_WIDTH = 1;
+input 	[IN34_WIDTH -1:0] In34;
+parameter IN35_WIDTH = 1;
+input 	[IN35_WIDTH -1:0] In35;
+parameter IN36_WIDTH = 1;
+input 	[IN36_WIDTH -1:0] In36;
+parameter IN37_WIDTH = 1;
+input 	[IN37_WIDTH -1:0] In37;
+parameter IN38_WIDTH = 1;
+input 	[IN38_WIDTH -1:0] In38;
+parameter IN39_WIDTH = 1;
+input 	[IN39_WIDTH -1:0] In39;
+parameter IN40_WIDTH = 1;
+input 	[IN40_WIDTH -1:0] In40;
+parameter IN41_WIDTH = 1;
+input 	[IN41_WIDTH -1:0] In41;
+parameter IN42_WIDTH = 1;
+input 	[IN42_WIDTH -1:0] In42;
+parameter IN43_WIDTH = 1;
+input 	[IN43_WIDTH -1:0] In43;
+parameter IN44_WIDTH = 1;
+input 	[IN44_WIDTH -1:0] In44;
+parameter IN45_WIDTH = 1;
+input 	[IN45_WIDTH -1:0] In45;
+parameter IN46_WIDTH = 1;
+input 	[IN46_WIDTH -1:0] In46;
+parameter IN47_WIDTH = 1;
+input 	[IN47_WIDTH -1:0] In47;
+parameter IN48_WIDTH = 1;
+input 	[IN48_WIDTH -1:0] In48;
+parameter IN49_WIDTH = 1;
+input 	[IN49_WIDTH -1:0] In49;
+parameter IN50_WIDTH = 1;
+input 	[IN50_WIDTH -1:0] In50;
+parameter IN51_WIDTH = 1;
+input 	[IN51_WIDTH -1:0] In51;
+parameter IN52_WIDTH = 1;
+input 	[IN52_WIDTH -1:0] In52;
+parameter IN53_WIDTH = 1;
+input 	[IN53_WIDTH -1:0] In53;
+parameter IN54_WIDTH = 1;
+input 	[IN54_WIDTH -1:0] In54;
+parameter IN55_WIDTH = 1;
+input 	[IN55_WIDTH -1:0] In55;
+parameter IN56_WIDTH = 1;
+input 	[IN56_WIDTH -1:0] In56;
+parameter IN57_WIDTH = 1;
+input 	[IN57_WIDTH -1:0] In57;
+parameter IN58_WIDTH = 1;
+input 	[IN58_WIDTH -1:0] In58;
+parameter IN59_WIDTH = 1;
+input 	[IN59_WIDTH -1:0] In59;
+parameter IN60_WIDTH = 1;
+input 	[IN60_WIDTH -1:0] In60;
+parameter IN61_WIDTH = 1;
+input 	[IN61_WIDTH -1:0] In61;
+parameter IN62_WIDTH = 1;
+input 	[IN62_WIDTH -1:0] In62;
+parameter IN63_WIDTH = 1;
+input 	[IN63_WIDTH -1:0] In63;
+parameter IN64_WIDTH = 1;
+input 	[IN64_WIDTH -1:0] In64;
+parameter IN65_WIDTH = 1;
+input 	[IN65_WIDTH -1:0] In65;
+parameter IN66_WIDTH = 1;
+input 	[IN66_WIDTH -1:0] In66;
+parameter IN67_WIDTH = 1;
+input 	[IN67_WIDTH -1:0] In67;
+parameter IN68_WIDTH = 1;
+input 	[IN68_WIDTH -1:0] In68;
+parameter IN69_WIDTH = 1;
+input 	[IN69_WIDTH -1:0] In69;
+parameter IN70_WIDTH = 1;
+input 	[IN70_WIDTH -1:0] In70;
+parameter IN71_WIDTH = 1;
+input 	[IN71_WIDTH -1:0] In71;
+parameter IN72_WIDTH = 1;
+input 	[IN72_WIDTH -1:0] In72;
+parameter IN73_WIDTH = 1;
+input 	[IN73_WIDTH -1:0] In73;
+parameter IN74_WIDTH = 1;
+input 	[IN74_WIDTH -1:0] In74;
+parameter IN75_WIDTH = 1;
+input 	[IN75_WIDTH -1:0] In75;
+parameter IN76_WIDTH = 1;
+input 	[IN76_WIDTH -1:0] In76;
+parameter IN77_WIDTH = 1;
+input 	[IN77_WIDTH -1:0] In77;
+parameter IN78_WIDTH = 1;
+input 	[IN78_WIDTH -1:0] In78;
+parameter IN79_WIDTH = 1;
+input 	[IN79_WIDTH -1:0] In79;
+parameter IN80_WIDTH = 1;
+input 	[IN80_WIDTH -1:0] In80;
+parameter IN81_WIDTH = 1;
+input 	[IN81_WIDTH -1:0] In81;
+parameter IN82_WIDTH = 1;
+input 	[IN82_WIDTH -1:0] In82;
+parameter IN83_WIDTH = 1;
+input 	[IN83_WIDTH -1:0] In83;
+parameter IN84_WIDTH = 1;
+input 	[IN84_WIDTH -1:0] In84;
+parameter IN85_WIDTH = 1;
+input 	[IN85_WIDTH -1:0] In85;
+parameter IN86_WIDTH = 1;
+input 	[IN86_WIDTH -1:0] In86;
+parameter IN87_WIDTH = 1;
+input 	[IN87_WIDTH -1:0] In87;
+parameter IN88_WIDTH = 1;
+input 	[IN88_WIDTH -1:0] In88;
+parameter IN89_WIDTH = 1;
+input 	[IN89_WIDTH -1:0] In89;
+parameter IN90_WIDTH = 1;
+input 	[IN90_WIDTH -1:0] In90;
+parameter IN91_WIDTH = 1;
+input 	[IN91_WIDTH -1:0] In91;
+parameter IN92_WIDTH = 1;
+input 	[IN92_WIDTH -1:0] In92;
+parameter IN93_WIDTH = 1;
+input 	[IN93_WIDTH -1:0] In93;
+parameter IN94_WIDTH = 1;
+input 	[IN94_WIDTH -1:0] In94;
+parameter IN95_WIDTH = 1;
+input 	[IN95_WIDTH -1:0] In95;
+parameter IN96_WIDTH = 1;
+input 	[IN96_WIDTH -1:0] In96;
+parameter IN97_WIDTH = 1;
+input 	[IN97_WIDTH -1:0] In97;
+parameter IN98_WIDTH = 1;
+input 	[IN98_WIDTH -1:0] In98;
+parameter IN99_WIDTH = 1;
+input 	[IN99_WIDTH -1:0] In99;
+parameter IN100_WIDTH = 1;
+input 	[IN100_WIDTH -1:0] In100;
+parameter IN101_WIDTH = 1;
+input 	[IN101_WIDTH -1:0] In101;
+parameter IN102_WIDTH = 1;
+input 	[IN102_WIDTH -1:0] In102;
+parameter IN103_WIDTH = 1;
+input 	[IN103_WIDTH -1:0] In103;
+parameter IN104_WIDTH = 1;
+input 	[IN104_WIDTH -1:0] In104;
+parameter IN105_WIDTH = 1;
+input 	[IN105_WIDTH -1:0] In105;
+parameter IN106_WIDTH = 1;
+input 	[IN106_WIDTH -1:0] In106;
+parameter IN107_WIDTH = 1;
+input 	[IN107_WIDTH -1:0] In107;
+parameter IN108_WIDTH = 1;
+input 	[IN108_WIDTH -1:0] In108;
+parameter IN109_WIDTH = 1;
+input 	[IN109_WIDTH -1:0] In109;
+parameter IN110_WIDTH = 1;
+input 	[IN110_WIDTH -1:0] In110;
+parameter IN111_WIDTH = 1;
+input 	[IN111_WIDTH -1:0] In111;
+parameter IN112_WIDTH = 1;
+input 	[IN112_WIDTH -1:0] In112;
+parameter IN113_WIDTH = 1;
+input 	[IN113_WIDTH -1:0] In113;
+parameter IN114_WIDTH = 1;
+input 	[IN114_WIDTH -1:0] In114;
+parameter IN115_WIDTH = 1;
+input 	[IN115_WIDTH -1:0] In115;
+parameter IN116_WIDTH = 1;
+input 	[IN116_WIDTH -1:0] In116;
+parameter IN117_WIDTH = 1;
+input 	[IN117_WIDTH -1:0] In117;
+parameter IN118_WIDTH = 1;
+input 	[IN118_WIDTH -1:0] In118;
+parameter IN119_WIDTH = 1;
+input 	[IN119_WIDTH -1:0] In119;
+parameter IN120_WIDTH = 1;
+input 	[IN120_WIDTH -1:0] In120;
+parameter IN121_WIDTH = 1;
+input 	[IN121_WIDTH -1:0] In121;
+parameter IN122_WIDTH = 1;
+input 	[IN122_WIDTH -1:0] In122;
+parameter IN123_WIDTH = 1;
+input 	[IN123_WIDTH -1:0] In123;
+parameter IN124_WIDTH = 1;
+input 	[IN124_WIDTH -1:0] In124;
+parameter IN125_WIDTH = 1;
+input 	[IN125_WIDTH -1:0] In125;
+parameter IN126_WIDTH = 1;
+input 	[IN126_WIDTH -1:0] In126;
+parameter IN127_WIDTH = 1;
+input 	[IN127_WIDTH -1:0] In127;
+parameter dout_width = 2;
+output [dout_width-1:0] dout;
+parameter NUM_PORTS =2;
+
+
+generate if (NUM_PORTS == 1)
+begin : C_NUM_1
+    assign dout = In0; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 2)
+begin : C_NUM_2
+    assign dout = {In1,In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 3)
+begin:C_NUM_3
+	assign dout = {In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 4)
+begin:C_NUM_4
+    assign dout = {In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 5)
+begin:C_NUM_5
+    assign dout = {In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 6)
+begin:C_NUM_6
+    assign dout = {In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 7)
+begin:C_NUM_7
+    assign dout = {In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 8)
+begin:C_NUM_8
+    assign dout = {In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 9)
+begin:C_NUM_9
+    assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 10)
+begin:C_NUM_10
+    assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 11)
+begin:C_NUM_11
+    assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 12)
+begin:C_NUM_12
+    assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 13)
+begin:C_NUM_13
+    assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 14)
+begin:C_NUM_14
+    assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 15)
+begin:C_NUM_15
+    assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 16)
+begin:C_NUM_16
+    assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 17)
+begin:C_NUM_17
+    assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 18)
+begin:C_NUM_18
+    assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 19)
+begin:C_NUM_19
+    assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 20)
+begin:C_NUM_20
+    assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 21)
+begin:C_NUM_21
+    assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 22)
+begin:C_NUM_22
+    assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 23)
+begin:C_NUM_23
+    assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 24)
+begin:C_NUM_24
+    assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 25)
+begin:C_NUM_25
+    assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 26)
+begin:C_NUM_26
+    assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 27)
+begin:C_NUM_27
+    assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 28)
+begin:C_NUM_28
+    assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 29)
+begin:C_NUM_29
+    assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 30)
+begin:C_NUM_30
+    assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 31)
+begin:C_NUM_31
+    assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 32)
+begin:C_NUM_32
+    assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 33)
+begin:C_NUM_33
+    assign dout = {In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 34)
+begin:C_NUM_34
+    assign dout = {In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 35)
+begin:C_NUM_35
+    assign dout = {In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 36)
+begin:C_NUM_36
+    assign dout = {In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 37)
+begin:C_NUM_37
+    assign dout = {In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 38)
+begin:C_NUM_38
+    assign dout = {In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 39)
+begin:C_NUM_39
+    assign dout = {In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 40)
+begin:C_NUM_40
+    assign dout = {In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 41)
+begin:C_NUM_41
+    assign dout = {In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 42)
+begin:C_NUM_42
+    assign dout = {In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 43)
+begin:C_NUM_43
+    assign dout = {In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 44)
+begin:C_NUM_44
+    assign dout = {In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 45)
+begin:C_NUM_45
+    assign dout = {In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 46)
+begin:C_NUM_46
+    assign dout = {In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 47)
+begin:C_NUM_47
+    assign dout = {In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 48)
+begin:C_NUM_48
+    assign dout = {In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 49)
+begin:C_NUM_49
+    assign dout = {In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 50)
+begin:C_NUM_50
+    assign dout = {In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 51)
+begin:C_NUM_51
+    assign dout = {In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 52)
+begin:C_NUM_52
+    assign dout = {In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 53)
+begin:C_NUM_53
+    assign dout = {In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 54)
+begin:C_NUM_54
+    assign dout = {In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 55)
+begin:C_NUM_55
+    assign dout = {In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 56)
+begin:C_NUM_56
+    assign dout = {In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 57)
+begin:C_NUM_57
+    assign dout = {In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 58)
+begin:C_NUM_58
+    assign dout = {In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 59)
+begin:C_NUM_59
+    assign dout = {In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 60)
+begin:C_NUM_60
+    assign dout = {In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 61)
+begin:C_NUM_61
+    assign dout = {In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 62)
+begin:C_NUM_62
+    assign dout = {In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 63)
+begin:C_NUM_63
+    assign dout = {In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 64)
+begin:C_NUM_64
+    assign dout = {In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 65)
+begin:C_NUM_65
+    assign dout = {In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 66)
+begin:C_NUM_66
+    assign dout = {In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 67)
+begin:C_NUM_67
+    assign dout = {In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 68)
+begin:C_NUM_68
+    assign dout = {In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 69)
+begin:C_NUM_69
+    assign dout = {In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 70)
+begin:C_NUM_70
+    assign dout = {In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 71)
+begin:C_NUM_71
+    assign dout = {In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 72)
+begin:C_NUM_72
+    assign dout = {In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 73)
+begin:C_NUM_73
+    assign dout = {In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 74)
+begin:C_NUM_74
+    assign dout = {In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 75)
+begin:C_NUM_75
+    assign dout = {In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 76)
+begin:C_NUM_76
+    assign dout = {In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 77)
+begin:C_NUM_77
+    assign dout = {In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 78)
+begin:C_NUM_78
+    assign dout = {In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 79)
+begin:C_NUM_79
+    assign dout = {In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 80)
+begin:C_NUM_80
+    assign dout = {In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 81)
+begin:C_NUM_81
+    assign dout = {In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 82)
+begin:C_NUM_82
+    assign dout = {In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 83)
+begin:C_NUM_83
+    assign dout = {In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 84)
+begin:C_NUM_84
+    assign dout = {In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 85)
+begin:C_NUM_85
+    assign dout = {In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 86)
+begin:C_NUM_86
+    assign dout = {In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 87)
+begin:C_NUM_87
+    assign dout = {In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 88)
+begin:C_NUM_88
+    assign dout = {In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 89)
+begin:C_NUM_89
+    assign dout = {In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 90)
+begin:C_NUM_90
+    assign dout = {In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 91)
+begin:C_NUM_91
+    assign dout = {In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 92)
+begin:C_NUM_92
+    assign dout = {In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 93)
+begin:C_NUM_93
+    assign dout = {In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 94)
+begin:C_NUM_94
+    assign dout = {In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 95)
+begin:C_NUM_95
+    assign dout = {In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 96)
+begin:C_NUM_96
+    assign dout = {In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 97)
+begin:C_NUM_97
+    assign dout = {In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 98)
+begin:C_NUM_98
+    assign dout = {In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 99)
+begin:C_NUM_99
+    assign dout = {In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 100)
+begin:C_NUM_100
+    assign dout = {In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 101)
+begin:C_NUM_101
+    assign dout = {In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 102)
+begin:C_NUM_102
+    assign dout = {In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 103)
+begin:C_NUM_103
+    assign dout = {In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 104)
+begin:C_NUM_104
+    assign dout = {In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 105)
+begin:C_NUM_105
+    assign dout = {In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 106)
+begin:C_NUM_106
+    assign dout = {In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 107)
+begin:C_NUM_107
+    assign dout = {In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 108)
+begin:C_NUM_108
+    assign dout = {In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 109)
+begin:C_NUM_109
+    assign dout = {In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 110)
+begin:C_NUM_110
+    assign dout = {In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 111)
+begin:C_NUM_111
+    assign dout = {In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 112)
+begin:C_NUM_112
+    assign dout = {In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 113)
+begin:C_NUM_113
+    assign dout = {In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 114)
+begin:C_NUM_114
+    assign dout = {In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 115)
+begin:C_NUM_115
+    assign dout = {In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 116)
+begin:C_NUM_116
+    assign dout = {In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 117)
+begin:C_NUM_117
+    assign dout = {In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 118)
+begin:C_NUM_118
+    assign dout = {In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 119)
+begin:C_NUM_119
+    assign dout = {In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 120)
+begin:C_NUM_120
+    assign dout = {In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 121)
+begin:C_NUM_121
+    assign dout = {In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 122)
+begin:C_NUM_122
+    assign dout = {In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 123)
+begin:C_NUM_123
+    assign dout = {In122,In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 124)
+begin:C_NUM_124
+    assign dout = {In123,In122,In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 125)
+begin:C_NUM_125
+    assign dout = {In124,In123,In122,In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 126)
+begin:C_NUM_126
+    assign dout = {In125,In124,In123,In122,In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 127)
+begin:C_NUM_127
+    assign dout = {In126,In125,In124,In123,In122,In121,In120,In119,In118,In117,In116,In115,In114,In113,In112,In111,In110,In109,In108,In107,In106,In105,In104,In103,In102,In101,In100,In99,In98,In97,In96,In95,In94,In93,In92,In91,In90,In89,In88,In87,In86,In85,In84,In83,In82,In81,In80,In79,In78,In77,In76,In75,In74,In73,In72,In71,In70,In69,In68,In67,In66,In65,In64,In63,In62,In61,In60,In59,In58,In57,In56,In55,In54,In53,In52,In51,In50,In49,In48,In47,In46,In45,In44,In43,In42,In41,In40,In39,In38,In37,In36,In35,In34,In33,In32,In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+endmodule
+
+
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v
new file mode 100644
index 0000000..51977ac
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v
@@ -0,0 +1,31 @@
+//------------------------------------------------------------------------

+//--

+//--  Filename      : xlconstant.v

+//--

+//--  Date          : 06/05/12

+//--

+//--  Description   : VERILOG description of a constant block.  This

+//--                  block does not use a core.

+//--

+//------------------------------------------------------------------------

+

+

+//------------------------------------------------------------------------

+//--

+//--  Module        : xlconstant

+//--

+//--  Architecture  : behavior

+//--

+//--  Description   : Top level VERILOG description of constant block

+//--

+//------------------------------------------------------------------------

+`timescale 1ps/1ps

+module xlconstant_v1_1_7_xlconstant (dout);

+	parameter CONST_VAL = 1;

+	parameter CONST_WIDTH = 1;

+	output [CONST_WIDTH-1:0] dout;

+

+	assign dout = CONST_VAL;

+endmodule

+
+
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/sim/design_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/sim/design_1.vhd
new file mode 100644
index 0000000..4fbeb11
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/sim/design_1.vhd
@@ -0,0 +1,581 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Jan 16 11:48:36 2024
+--Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M1_decodeur_i2s_imp_17RYJKZ is
+  port (
+    clk : in STD_LOGIC;
+    i_data : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat_left : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat_right : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_str_dat : out STD_LOGIC
+  );
+end M1_decodeur_i2s_imp_17RYJKZ;
+
+architecture STRUCTURE of M1_decodeur_i2s_imp_17RYJKZ is
+  component design_1_compteur_nbits_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_0;
+  component design_1_mef_decod_i2s_v1b_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_str_dat : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_decod_i2s_v1b_0_0;
+  component design_1_reg_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_0;
+  component design_1_reg_24b_0_1 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_1;
+  component design_1_reg_dec_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_0_0;
+  component design_1_xlconstant_0_2 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_2;
+  component design_1_xlconstant_0_3 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_xlconstant_0_3;
+  signal clk_1 : STD_LOGIC;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_bit_enable : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_left : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_right : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_str_dat : STD_LOGIC;
+  signal reg_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_24b_1_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
+begin
+  clk_1 <= clk;
+  i_data_1 <= i_data;
+  i_lrc_1 <= i_lrc;
+  i_reset_1 <= i_reset;
+  o_dat_left(23 downto 0) <= reg_24b_1_o_dat(23 downto 0);
+  o_dat_right(23 downto 0) <= reg_24b_0_o_dat(23 downto 0);
+  o_str_dat <= mef_decod_i2s_v1b_0_o_str_dat;
+MEF_decodeur_i2s: component design_1_mef_decod_i2s_v1b_0_0
+     port map (
+      i_bclk => clk_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_bit_enable => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_cpt_bit_reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset,
+      o_load_left => mef_decod_i2s_v1b_0_o_load_left,
+      o_load_right => mef_decod_i2s_v1b_0_o_load_right,
+      o_str_dat => mef_decod_i2s_v1b_0_o_str_dat
+    );
+compteur_7bits: component design_1_compteur_nbits_0_0
+     port map (
+      clk => clk_1,
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset
+    );
+registre_24bits_droite: component design_1_reg_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_right,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_0_o_dat(23 downto 0)
+    );
+registre_24bits_gauche: component design_1_reg_24b_0_1
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_left,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_1_o_dat(23 downto 0)
+    );
+registre_decalage_24bits: component design_1_reg_dec_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat_bit => i_data_1,
+      i_dat_load(23 downto 0) => xlconstant_1_dout(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      i_load => xlconstant_0_dout(0),
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_2
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlconstant_1: component design_1_xlconstant_0_3
+     port map (
+      dout(23 downto 0) => xlconstant_1_dout(23 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M9_codeur_i2s_imp_1VJCTGL is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_dat_left : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_dat_right : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end M9_codeur_i2s_imp_1VJCTGL;
+
+architecture STRUCTURE of M9_codeur_i2s_imp_1VJCTGL is
+  component design_1_compteur_nbits_0_1 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_1;
+  component design_1_mef_cod_i2s_vsb_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_cod_i2s_vsb_0_0;
+  component design_1_mux2_0_0 is
+  port (
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux2_0_0;
+  component design_1_reg_dec_24b_fd_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_fd_0_0;
+  component design_1_util_vector_logic_0_0 is
+  port (
+    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_util_vector_logic_0_0;
+  component design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_xlconcat_0_0;
+  component design_1_xlconstant_0_1 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_1;
+  component design_1_xlslice_0_0 is
+  port (
+    Din : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlslice_0_0;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_bclk_0_1 : STD_LOGIC;
+  signal i_lrc_0_1 : STD_LOGIC;
+  signal i_reset_0_1 : STD_LOGIC;
+  signal input1_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal input2_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal mef_cod_i2s_vsb_0_o_bit_enable : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_left : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_right : STD_LOGIC;
+  signal mux2_0_output : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_fd_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  i_bclk_0_1 <= i_bclk;
+  i_lrc_0_1 <= i_lrc;
+  i_reset_0_1 <= i_reset;
+  input1_0_1(23 downto 0) <= i_dat_left(23 downto 0);
+  input2_0_1(23 downto 0) <= i_dat_right(23 downto 0);
+  o_dat(0) <= xlslice_0_Dout(0);
+compteur_nbits_0: component design_1_compteur_nbits_0_1
+     port map (
+      clk => i_bclk_0_1,
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset
+    );
+mef_cod_i2s_vsb_0: component design_1_mef_cod_i2s_vsb_0_0
+     port map (
+      i_bclk => i_bclk_0_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_0_1,
+      i_reset => i_reset_0_1,
+      o_bit_enable => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_cpt_bit_reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset,
+      o_load_left => mef_cod_i2s_vsb_0_o_load_left,
+      o_load_right => mef_cod_i2s_vsb_0_o_load_right
+    );
+mux2_0: component design_1_mux2_0_0
+     port map (
+      input1(23 downto 0) => input1_0_1(23 downto 0),
+      input2(23 downto 0) => input2_0_1(23 downto 0),
+      output0(23 downto 0) => mux2_0_output(23 downto 0),
+      sel(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+reg_dec_24b_fd_0: component design_1_reg_dec_24b_fd_0_0
+     port map (
+      i_clk => i_bclk_0_1,
+      i_dat_bit => xlconstant_0_dout(0),
+      i_dat_load(23 downto 0) => mux2_0_output(23 downto 0),
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      i_load => util_vector_logic_0_Res(0),
+      i_reset => i_reset_0_1,
+      o_dat(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0)
+    );
+util_vector_logic_0: component design_1_util_vector_logic_0_0
+     port map (
+      Op1(0) => mef_cod_i2s_vsb_0_o_load_left,
+      Op2(0) => mef_cod_i2s_vsb_0_o_load_right,
+      Res(0) => util_vector_logic_0_Res(0)
+    );
+xlconcat_0: component design_1_xlconcat_0_0
+     port map (
+      In0(0) => mef_cod_i2s_vsb_0_o_load_left,
+      In1(0) => mef_cod_i2s_vsb_0_o_load_right,
+      dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_1
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlslice_0: component design_1_xlslice_0_0
+     port map (
+      Din(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0),
+      Dout(0) => xlslice_0_Dout(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- Modules à modifier:
+  -- MEF_decodeur_i2s (dans M1_decodeur_i2s)
+  -- M5_parametre_1
+  -- M6_parametre_2
+  -- M8_commande
+  -- Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+  -- et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+  entity design_1 is
+  port (
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_recdat : in STD_LOGIC;
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=28,numReposBlks=26,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=19,numPkgbdBlks=0,bdsource=USER,""""""""""""""""""""""""""""""""""""""""""""""""""""da_clkrst_cnt""""""""""""""""""""""""""""""""""""""""""""""""""""=1,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_affhexPmodSSD_v3_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    DA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_affhexPmodSSD_v3_0_0;
+  component design_1_calcul_param_1_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_1_0_0;
+  component design_1_calcul_param_2_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_2_0_0;
+  component design_1_calcul_param_3_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_3_0_0;
+  component design_1_mux4_0_0 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux4_0_0;
+  component design_1_mux4_0_1 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_mux4_0_1;
+  component design_1_sig_fct_3_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_3_0_0;
+  component design_1_sig_fct_sat_dure_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_0;
+  component design_1_sig_fct_sat_dure_0_1 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_1;
+  component design_1_xlconstant_0_0 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_xlconstant_0_0;
+  component design_1_module_commande_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    o_reset : out STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_btn_cd : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_selection_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_selection_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_module_commande_0_0;
+  signal M10_conversion_affichage_JPmod : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal M8_commande_o_btn_cd : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal M8_commande_o_selection_par : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal M9_codeur_i2s_o_dat : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal calcul_param_1_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_2_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_3_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal clk_1 : STD_LOGIC;
+  signal decodeur_i2s_o_dat_right : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal decodeur_i2s_o_str_dat : STD_LOGIC;
+  signal i_btn_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal i_dat_left_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_dat_right_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal i_sw_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal module_commande_0_o_selection_fct : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal mux4_1_output : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal sig_fct_3_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_1_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_100MHz : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_100MHZ CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_100MHz : signal is "XIL_INTERFACENAME CLK.CLK_100MHZ, CLK_DOMAIN design_1_clk_100MHz, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
+begin
+  JPmod(7 downto 0) <= M10_conversion_affichage_JPmod(7 downto 0);
+  clk_1 <= clk_100MHz;
+  i_btn_1(3 downto 0) <= i_btn(3 downto 0);
+  i_data_1 <= i_recdat;
+  i_lrc_1 <= i_lrc;
+  i_sw_1(3 downto 0) <= i_sw(3 downto 0);
+  o_param(7 downto 0) <= mux4_1_output(7 downto 0);
+  o_pbdat(0) <= M9_codeur_i2s_o_dat(0);
+  o_sel_fct(1 downto 0) <= module_commande_0_o_selection_fct(1 downto 0);
+  o_sel_par(1 downto 0) <= M8_commande_o_selection_par(1 downto 0);
+M10_conversion_affichage: component design_1_affhexPmodSSD_v3_0_0
+     port map (
+      DA(7 downto 0) => mux4_1_output(7 downto 0),
+      JPmod(7 downto 0) => M10_conversion_affichage_JPmod(7 downto 0),
+      clk => clk_1,
+      i_btn(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      reset => i_reset_1
+    );
+M1_decodeur_i2s: entity work.M1_decodeur_i2s_imp_17RYJKZ
+     port map (
+      clk => clk_1,
+      i_data => i_data_1,
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      o_dat_right(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_str_dat => decodeur_i2s_o_str_dat
+    );
+M2_fonction_distortion_dure1: component design_1_sig_fct_sat_dure_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0)
+    );
+M3_fonction_distorsion_dure2: component design_1_sig_fct_sat_dure_0_1
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0)
+    );
+M4_fonction3: component design_1_sig_fct_3_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0)
+    );
+M5_parametre_1: component design_1_calcul_param_1_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_1_0_o_param(7 downto 0)
+    );
+M6_parametre_2: component design_1_calcul_param_2_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_2_0_o_param(7 downto 0)
+    );
+M7_parametre_3: component design_1_calcul_param_3_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_3_0_o_param(7 downto 0)
+    );
+M8_commande: component design_1_module_commande_0_0
+     port map (
+      clk => clk_1,
+      i_btn(3 downto 0) => i_btn_1(3 downto 0),
+      i_sw(3 downto 0) => i_sw_1(3 downto 0),
+      o_btn_cd(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      o_reset => i_reset_1,
+      o_selection_fct(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0),
+      o_selection_par(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+M9_codeur_i2s: entity work.M9_codeur_i2s_imp_1VJCTGL
+     port map (
+      i_bclk => clk_1,
+      i_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      i_dat_right(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat(0) => M9_codeur_i2s_o_dat(0)
+    );
+Multiplexeur_choix_fonction: component design_1_mux4_0_0
+     port map (
+      input0(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      input1(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0),
+      input2(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0),
+      input3(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0),
+      output0(23 downto 0) => i_dat_right_1(23 downto 0),
+      sel(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0)
+    );
+Multiplexeur_choix_parametre: component design_1_mux4_0_1
+     port map (
+      input0(7 downto 0) => xlconstant_0_dout(7 downto 0),
+      input1(7 downto 0) => calcul_param_1_0_o_param(7 downto 0),
+      input2(7 downto 0) => calcul_param_2_0_o_param(7 downto 0),
+      input3(7 downto 0) => calcul_param_3_0_o_param(7 downto 0),
+      output0(7 downto 0) => mux4_1_output(7 downto 0),
+      sel(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+parametre_0: component design_1_xlconstant_0_0
+     port map (
+      dout(7 downto 0) => xlconstant_0_dout(7 downto 0)
+    );
+end STRUCTURE;
diff --git a/pb_logique_seq.gen/sources_1/bd/design_1/synth/design_1.vhd b/pb_logique_seq.gen/sources_1/bd/design_1/synth/design_1.vhd
new file mode 100644
index 0000000..4fbeb11
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/design_1/synth/design_1.vhd
@@ -0,0 +1,581 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Jan 16 11:48:36 2024
+--Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M1_decodeur_i2s_imp_17RYJKZ is
+  port (
+    clk : in STD_LOGIC;
+    i_data : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat_left : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat_right : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_str_dat : out STD_LOGIC
+  );
+end M1_decodeur_i2s_imp_17RYJKZ;
+
+architecture STRUCTURE of M1_decodeur_i2s_imp_17RYJKZ is
+  component design_1_compteur_nbits_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_0;
+  component design_1_mef_decod_i2s_v1b_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_str_dat : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_decod_i2s_v1b_0_0;
+  component design_1_reg_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_0;
+  component design_1_reg_24b_0_1 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_1;
+  component design_1_reg_dec_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_0_0;
+  component design_1_xlconstant_0_2 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_2;
+  component design_1_xlconstant_0_3 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_xlconstant_0_3;
+  signal clk_1 : STD_LOGIC;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_bit_enable : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_left : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_right : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_str_dat : STD_LOGIC;
+  signal reg_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_24b_1_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
+begin
+  clk_1 <= clk;
+  i_data_1 <= i_data;
+  i_lrc_1 <= i_lrc;
+  i_reset_1 <= i_reset;
+  o_dat_left(23 downto 0) <= reg_24b_1_o_dat(23 downto 0);
+  o_dat_right(23 downto 0) <= reg_24b_0_o_dat(23 downto 0);
+  o_str_dat <= mef_decod_i2s_v1b_0_o_str_dat;
+MEF_decodeur_i2s: component design_1_mef_decod_i2s_v1b_0_0
+     port map (
+      i_bclk => clk_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_bit_enable => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_cpt_bit_reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset,
+      o_load_left => mef_decod_i2s_v1b_0_o_load_left,
+      o_load_right => mef_decod_i2s_v1b_0_o_load_right,
+      o_str_dat => mef_decod_i2s_v1b_0_o_str_dat
+    );
+compteur_7bits: component design_1_compteur_nbits_0_0
+     port map (
+      clk => clk_1,
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset
+    );
+registre_24bits_droite: component design_1_reg_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_right,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_0_o_dat(23 downto 0)
+    );
+registre_24bits_gauche: component design_1_reg_24b_0_1
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_left,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_1_o_dat(23 downto 0)
+    );
+registre_decalage_24bits: component design_1_reg_dec_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat_bit => i_data_1,
+      i_dat_load(23 downto 0) => xlconstant_1_dout(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      i_load => xlconstant_0_dout(0),
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_2
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlconstant_1: component design_1_xlconstant_0_3
+     port map (
+      dout(23 downto 0) => xlconstant_1_dout(23 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M9_codeur_i2s_imp_1VJCTGL is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_dat_left : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_dat_right : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end M9_codeur_i2s_imp_1VJCTGL;
+
+architecture STRUCTURE of M9_codeur_i2s_imp_1VJCTGL is
+  component design_1_compteur_nbits_0_1 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_1;
+  component design_1_mef_cod_i2s_vsb_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_cod_i2s_vsb_0_0;
+  component design_1_mux2_0_0 is
+  port (
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux2_0_0;
+  component design_1_reg_dec_24b_fd_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_fd_0_0;
+  component design_1_util_vector_logic_0_0 is
+  port (
+    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_util_vector_logic_0_0;
+  component design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_xlconcat_0_0;
+  component design_1_xlconstant_0_1 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_1;
+  component design_1_xlslice_0_0 is
+  port (
+    Din : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlslice_0_0;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_bclk_0_1 : STD_LOGIC;
+  signal i_lrc_0_1 : STD_LOGIC;
+  signal i_reset_0_1 : STD_LOGIC;
+  signal input1_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal input2_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal mef_cod_i2s_vsb_0_o_bit_enable : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_left : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_right : STD_LOGIC;
+  signal mux2_0_output : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_fd_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  i_bclk_0_1 <= i_bclk;
+  i_lrc_0_1 <= i_lrc;
+  i_reset_0_1 <= i_reset;
+  input1_0_1(23 downto 0) <= i_dat_left(23 downto 0);
+  input2_0_1(23 downto 0) <= i_dat_right(23 downto 0);
+  o_dat(0) <= xlslice_0_Dout(0);
+compteur_nbits_0: component design_1_compteur_nbits_0_1
+     port map (
+      clk => i_bclk_0_1,
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset
+    );
+mef_cod_i2s_vsb_0: component design_1_mef_cod_i2s_vsb_0_0
+     port map (
+      i_bclk => i_bclk_0_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_0_1,
+      i_reset => i_reset_0_1,
+      o_bit_enable => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_cpt_bit_reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset,
+      o_load_left => mef_cod_i2s_vsb_0_o_load_left,
+      o_load_right => mef_cod_i2s_vsb_0_o_load_right
+    );
+mux2_0: component design_1_mux2_0_0
+     port map (
+      input1(23 downto 0) => input1_0_1(23 downto 0),
+      input2(23 downto 0) => input2_0_1(23 downto 0),
+      output0(23 downto 0) => mux2_0_output(23 downto 0),
+      sel(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+reg_dec_24b_fd_0: component design_1_reg_dec_24b_fd_0_0
+     port map (
+      i_clk => i_bclk_0_1,
+      i_dat_bit => xlconstant_0_dout(0),
+      i_dat_load(23 downto 0) => mux2_0_output(23 downto 0),
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      i_load => util_vector_logic_0_Res(0),
+      i_reset => i_reset_0_1,
+      o_dat(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0)
+    );
+util_vector_logic_0: component design_1_util_vector_logic_0_0
+     port map (
+      Op1(0) => mef_cod_i2s_vsb_0_o_load_left,
+      Op2(0) => mef_cod_i2s_vsb_0_o_load_right,
+      Res(0) => util_vector_logic_0_Res(0)
+    );
+xlconcat_0: component design_1_xlconcat_0_0
+     port map (
+      In0(0) => mef_cod_i2s_vsb_0_o_load_left,
+      In1(0) => mef_cod_i2s_vsb_0_o_load_right,
+      dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_1
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlslice_0: component design_1_xlslice_0_0
+     port map (
+      Din(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0),
+      Dout(0) => xlslice_0_Dout(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- Modules à modifier:
+  -- MEF_decodeur_i2s (dans M1_decodeur_i2s)
+  -- M5_parametre_1
+  -- M6_parametre_2
+  -- M8_commande
+  -- Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+  -- et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+  entity design_1 is
+  port (
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_recdat : in STD_LOGIC;
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=28,numReposBlks=26,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=19,numPkgbdBlks=0,bdsource=USER,""""""""""""""""""""""""""""""""""""""""""""""""""""da_clkrst_cnt""""""""""""""""""""""""""""""""""""""""""""""""""""=1,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_affhexPmodSSD_v3_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    DA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_affhexPmodSSD_v3_0_0;
+  component design_1_calcul_param_1_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_1_0_0;
+  component design_1_calcul_param_2_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_2_0_0;
+  component design_1_calcul_param_3_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_3_0_0;
+  component design_1_mux4_0_0 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux4_0_0;
+  component design_1_mux4_0_1 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_mux4_0_1;
+  component design_1_sig_fct_3_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_3_0_0;
+  component design_1_sig_fct_sat_dure_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_0;
+  component design_1_sig_fct_sat_dure_0_1 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_1;
+  component design_1_xlconstant_0_0 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_xlconstant_0_0;
+  component design_1_module_commande_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    o_reset : out STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_btn_cd : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_selection_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_selection_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_module_commande_0_0;
+  signal M10_conversion_affichage_JPmod : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal M8_commande_o_btn_cd : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal M8_commande_o_selection_par : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal M9_codeur_i2s_o_dat : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal calcul_param_1_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_2_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_3_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal clk_1 : STD_LOGIC;
+  signal decodeur_i2s_o_dat_right : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal decodeur_i2s_o_str_dat : STD_LOGIC;
+  signal i_btn_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal i_dat_left_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_dat_right_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal i_sw_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal module_commande_0_o_selection_fct : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal mux4_1_output : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal sig_fct_3_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_1_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_100MHz : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_100MHZ CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_100MHz : signal is "XIL_INTERFACENAME CLK.CLK_100MHZ, CLK_DOMAIN design_1_clk_100MHz, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
+begin
+  JPmod(7 downto 0) <= M10_conversion_affichage_JPmod(7 downto 0);
+  clk_1 <= clk_100MHz;
+  i_btn_1(3 downto 0) <= i_btn(3 downto 0);
+  i_data_1 <= i_recdat;
+  i_lrc_1 <= i_lrc;
+  i_sw_1(3 downto 0) <= i_sw(3 downto 0);
+  o_param(7 downto 0) <= mux4_1_output(7 downto 0);
+  o_pbdat(0) <= M9_codeur_i2s_o_dat(0);
+  o_sel_fct(1 downto 0) <= module_commande_0_o_selection_fct(1 downto 0);
+  o_sel_par(1 downto 0) <= M8_commande_o_selection_par(1 downto 0);
+M10_conversion_affichage: component design_1_affhexPmodSSD_v3_0_0
+     port map (
+      DA(7 downto 0) => mux4_1_output(7 downto 0),
+      JPmod(7 downto 0) => M10_conversion_affichage_JPmod(7 downto 0),
+      clk => clk_1,
+      i_btn(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      reset => i_reset_1
+    );
+M1_decodeur_i2s: entity work.M1_decodeur_i2s_imp_17RYJKZ
+     port map (
+      clk => clk_1,
+      i_data => i_data_1,
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      o_dat_right(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_str_dat => decodeur_i2s_o_str_dat
+    );
+M2_fonction_distortion_dure1: component design_1_sig_fct_sat_dure_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0)
+    );
+M3_fonction_distorsion_dure2: component design_1_sig_fct_sat_dure_0_1
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0)
+    );
+M4_fonction3: component design_1_sig_fct_3_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0)
+    );
+M5_parametre_1: component design_1_calcul_param_1_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_1_0_o_param(7 downto 0)
+    );
+M6_parametre_2: component design_1_calcul_param_2_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_2_0_o_param(7 downto 0)
+    );
+M7_parametre_3: component design_1_calcul_param_3_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_3_0_o_param(7 downto 0)
+    );
+M8_commande: component design_1_module_commande_0_0
+     port map (
+      clk => clk_1,
+      i_btn(3 downto 0) => i_btn_1(3 downto 0),
+      i_sw(3 downto 0) => i_sw_1(3 downto 0),
+      o_btn_cd(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      o_reset => i_reset_1,
+      o_selection_fct(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0),
+      o_selection_par(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+M9_codeur_i2s: entity work.M9_codeur_i2s_imp_1VJCTGL
+     port map (
+      i_bclk => clk_1,
+      i_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      i_dat_right(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat(0) => M9_codeur_i2s_o_dat(0)
+    );
+Multiplexeur_choix_fonction: component design_1_mux4_0_0
+     port map (
+      input0(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      input1(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0),
+      input2(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0),
+      input3(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0),
+      output0(23 downto 0) => i_dat_right_1(23 downto 0),
+      sel(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0)
+    );
+Multiplexeur_choix_parametre: component design_1_mux4_0_1
+     port map (
+      input0(7 downto 0) => xlconstant_0_dout(7 downto 0),
+      input1(7 downto 0) => calcul_param_1_0_o_param(7 downto 0),
+      input2(7 downto 0) => calcul_param_2_0_o_param(7 downto 0),
+      input3(7 downto 0) => calcul_param_3_0_o_param(7 downto 0),
+      output0(7 downto 0) => mux4_1_output(7 downto 0),
+      sel(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+parametre_0: component design_1_xlconstant_0_0
+     port map (
+      dout(7 downto 0) => xlconstant_0_dout(7 downto 0)
+    );
+end STRUCTURE;
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml
new file mode 100644
index 0000000..4889a41
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/component.xml
@@ -0,0 +1,215 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>affhexPmodSSD_v3</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>affhexPmodSSD_v3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>b762c3ee</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>affhexPmodSSD_v3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>b762c3ee</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>DA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>JPmod</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>const_CLK_Hz</spirit:name>
+        <spirit:displayName>Const Clk Hz</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/affhexPmodSSD_v3_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_e6d8f77e</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:affhexPmodSSD_v3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>const_CLK_Hz</spirit:name>
+      <spirit:displayName>Const Clk Hz</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.const_CLK_Hz">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">affhexPmodSSD_v3_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>affhexPmodSSD_v3_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:08Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl
new file mode 100644
index 0000000..908e4b1
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/affhexPmodSSD_v3/xgui/affhexPmodSSD_v3_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "const_CLK_Hz" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.const_CLK_Hz { PARAM_VALUE.const_CLK_Hz } {

+	# Procedure called to update const_CLK_Hz when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.const_CLK_Hz { PARAM_VALUE.const_CLK_Hz } {

+	# Procedure called to validate const_CLK_Hz

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.const_CLK_Hz { MODELPARAM_VALUE.const_CLK_Hz PARAM_VALUE.const_CLK_Hz } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.const_CLK_Hz}] ${MODELPARAM_VALUE.const_CLK_Hz}

+}

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/component.xml
new file mode 100644
index 0000000..6840ad3
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/component.xml
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>calcul_param_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_1</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d28c5364</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_1</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d28c5364</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/calcul_param_1_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_1:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">calcul_param_1_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>calcul_param_1_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/xgui/calcul_param_1_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/xgui/calcul_param_1_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_1/xgui/calcul_param_1_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/component.xml
new file mode 100644
index 0000000..fd4b31c
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/component.xml
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>calcul_param_2</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>6cdade35</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>6cdade35</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/calcul_param_2_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">calcul_param_2_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>calcul_param_2_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/xgui/calcul_param_2_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/xgui/calcul_param_2_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_2/xgui/calcul_param_2_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/component.xml
new file mode 100644
index 0000000..9e638e7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/component.xml
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>calcul_param_3</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d76edf2d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>calcul_param_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d76edf2d</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_param</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/calcul_param_3_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:calcul_param_3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">calcul_param_3_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>calcul_param_3_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/xgui/calcul_param_3_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/xgui/calcul_param_3_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/calcul_param_3/xgui/calcul_param_3_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/component.xml
new file mode 100644
index 0000000..216012a
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/component.xml
@@ -0,0 +1,194 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>compteur_nbits</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">reset</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>249e7abe</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>compteur_nbits</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>249e7abe</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_val_cpt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbits&apos;)) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbits</spirit:name>
+        <spirit:displayName>Nbits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbits">8</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/compteur_nbits_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_912d28ee</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:compteur_nbits:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbits</spirit:name>
+      <spirit:displayName>Nbits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbits">8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">compteur_nbits_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>compteur_nbits_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/xgui/compteur_nbits_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/xgui/compteur_nbits_v1_0.tcl
new file mode 100644
index 0000000..7c3ed37
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/compteur_nbits/xgui/compteur_nbits_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "nbits" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.nbits { PARAM_VALUE.nbits } {

+	# Procedure called to update nbits when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.nbits { PARAM_VALUE.nbits } {

+	# Procedure called to validate nbits

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.nbits { MODELPARAM_VALUE.nbits PARAM_VALUE.nbits } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.nbits}] ${MODELPARAM_VALUE.nbits}

+}

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/component.xml
new file mode 100644
index 0000000..3dba9c7
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/component.xml
@@ -0,0 +1,228 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>mef_cod_i2s_vsb</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mef_cod_i2s_vsb</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>139c27c1</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mef_cod_i2s_vsb</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>139c27c1</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_lrc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_cpt_bits</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_bit_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_left</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_right</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_cpt_bit_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mef_cod_i2s_vsb_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mef_cod_i2s_vsb:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mef_cod_i2s_vsb_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>mef_cod_i2s_vsb_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/xgui/mef_cod_i2s_vsb_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/xgui/mef_cod_i2s_vsb_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mef_cod_i2s_vsb/xgui/mef_cod_i2s_vsb_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/component.xml
new file mode 100644
index 0000000..9e98083
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/component.xml
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>mef_decod_i2s_v1b</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>o_cpt_bit_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_cpt_bit_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mef_decod_i2s_v1b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c2f641a2</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mef_decod_i2s_v1b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c2f641a2</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_bclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_lrc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_cpt_bits</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">6</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_bit_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_left</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_load_right</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_str_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_cpt_bit_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mef_decod_i2s_v1b_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mef_decod_i2s_v1b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mef_decod_i2s_v1b_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>mef_decod_i2s_v1b_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:09Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/xgui/mef_decod_i2s_v1b_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/xgui/mef_decod_i2s_v1b_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mef_decod_i2s_v1b/xgui/mef_decod_i2s_v1b_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/module_commande/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/module_commande/component.xml
new file mode 100644
index 0000000..1a28f64
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/module_commande/component.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>module_commande</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>o_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>o_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>module_commande</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>2df8a718</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>module_commande</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>2df8a718</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_btn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_sw</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_btn_cd</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.nbtn&apos;)) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_selection_par</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>nbtn</spirit:name>
+        <spirit:displayName>Nbtn</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nbtn">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>mode_simulation</spirit:name>
+        <spirit:displayName>Mode Simulation</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/module_commande_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_98c0d650</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:module_commande:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>nbtn</spirit:name>
+      <spirit:displayName>Nbtn</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.nbtn">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mode_simulation</spirit:name>
+      <spirit:displayName>Mode Simulation</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.mode_simulation" spirit:bitStringLength="1">&quot;0&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">module_commande_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>module_commande_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2024-01-16T16:44:59Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/module_commande/xgui/module_commande_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/module_commande/xgui/module_commande_v1_0.tcl
new file mode 100644
index 0000000..9206ace
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/module_commande/xgui/module_commande_v1_0.tcl
@@ -0,0 +1,40 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "mode_simulation" -parent ${Page_0}

+  ipgui::add_param $IPINST -name "nbtn" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.mode_simulation { PARAM_VALUE.mode_simulation } {

+	# Procedure called to update mode_simulation when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.mode_simulation { PARAM_VALUE.mode_simulation } {

+	# Procedure called to validate mode_simulation

+	return true

+}

+

+proc update_PARAM_VALUE.nbtn { PARAM_VALUE.nbtn } {

+	# Procedure called to update nbtn when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.nbtn { PARAM_VALUE.nbtn } {

+	# Procedure called to validate nbtn

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.nbtn { MODELPARAM_VALUE.nbtn PARAM_VALUE.nbtn } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.nbtn}] ${MODELPARAM_VALUE.nbtn}

+}

+

+proc update_MODELPARAM_VALUE.mode_simulation { MODELPARAM_VALUE.mode_simulation PARAM_VALUE.mode_simulation } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.mode_simulation}] ${MODELPARAM_VALUE.mode_simulation}

+}

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mux2/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/mux2/component.xml
new file mode 100644
index 0000000..f10d90f
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mux2/component.xml
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>mux2</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mux2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d3169f7e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mux2</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>d3169f7e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">24</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mux2_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_6aef23ef</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mux2:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mux2_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>mux2_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:10Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mux2/xgui/mux2_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/mux2/xgui/mux2_v1_0.tcl
new file mode 100644
index 0000000..6fa9bef
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mux2/xgui/mux2_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "input_length" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.input_length { PARAM_VALUE.input_length } {

+	# Procedure called to update input_length when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.input_length { PARAM_VALUE.input_length } {

+	# Procedure called to validate input_length

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.input_length { MODELPARAM_VALUE.input_length PARAM_VALUE.input_length } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.input_length}] ${MODELPARAM_VALUE.input_length}

+}

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mux4/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/mux4/component.xml
new file mode 100644
index 0000000..674ef39
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mux4/component.xml
@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>mux4</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>35010ed3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>mux4</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>35010ed3</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>input0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>input3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>output0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.input_length&apos;)) - 1)">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>input_length</spirit:name>
+        <spirit:displayName>Input Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.input_length">24</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mux4_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_6aef23ef</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:mux4:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>input_length</spirit:name>
+      <spirit:displayName>Input Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.input_length">24</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mux4_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>mux4_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:10Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/mux4/xgui/mux4_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/mux4/xgui/mux4_v1_0.tcl
new file mode 100644
index 0000000..6fa9bef
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/mux4/xgui/mux4_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "input_length" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.input_length { PARAM_VALUE.input_length } {

+	# Procedure called to update input_length when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.input_length { PARAM_VALUE.input_length } {

+	# Procedure called to validate input_length

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.input_length { MODELPARAM_VALUE.input_length PARAM_VALUE.input_length } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.input_length}] ${MODELPARAM_VALUE.input_length}

+}

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/component.xml
new file mode 100644
index 0000000..2215507
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/component.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>reg_24b</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>34a41093</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>34a41093</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/reg_24b_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">reg_24b_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>reg_24b_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:10Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/xgui/reg_24b_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/xgui/reg_24b_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_24b/xgui/reg_24b_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/component.xml
new file mode 100644
index 0000000..c008430
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/component.xml
@@ -0,0 +1,225 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>reg_dec_24b</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_dec_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c6e83b81</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_dec_24b</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c6e83b81</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_bit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/reg_dec_24b_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_dec_24b:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">reg_dec_24b_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>reg_dec_24b_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:10Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/xgui/reg_dec_24b_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/xgui/reg_dec_24b_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b/xgui/reg_dec_24b_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/component.xml
new file mode 100644
index 0000000..b63a928
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/component.xml
@@ -0,0 +1,225 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>reg_dec_24b_fd</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_RESET">i_reset</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_dec_24b_fd</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>1bfc1b4e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>reg_dec_24b_fd</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>1bfc1b4e</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_bit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>i_dat_load</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_dat</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/reg_dec_24b_fd_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:reg_dec_24b_fd:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">reg_dec_24b_fd_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>reg_dec_24b_fd_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:11Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/xgui/reg_dec_24b_fd_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/xgui/reg_dec_24b_fd_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/reg_dec_24b_fd/xgui/reg_dec_24b_fd_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/component.xml
new file mode 100644
index 0000000..c94c838
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/component.xml
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>sig_fct_3</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>sig_fct_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c71cbbbb</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>sig_fct_3</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>c71cbbbb</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/sig_fct_3_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:sig_fct_3:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">sig_fct_3_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>sig_fct_3_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:11Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/xgui/sig_fct_3_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/xgui/sig_fct_3_v1_0.tcl
new file mode 100644
index 0000000..66195ab
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_3/xgui/sig_fct_3_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  ipgui::add_page $IPINST -name "Page 0"

+

+

+}

+

+

diff --git a/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/component.xml b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/component.xml
new file mode 100644
index 0000000..ed85434
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/component.xml
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>sig_fct_sat_dure</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>sig_fct_sat_dure</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>824df50f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>sig_fct_sat_dure</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>824df50f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>i_ech</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>o_ech_fct</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">23</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="unsigned(23 downto 0)">
+        <spirit:name>c_ech_u24_max</spirit:name>
+        <spirit:displayName>C Ech U24 Max</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/sig_fct_sat_dure_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_3d12ea57</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:sig_fct_sat_dure:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>c_ech_u24_max</spirit:name>
+      <spirit:displayName>C Ech U24 Max</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.c_ech_u24_max" spirit:bitStringLength="24">0x1FFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">sig_fct_sat_dure_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>sig_fct_sat_dure_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-01-24T13:37:11Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/xgui/sig_fct_sat_dure_v1_0.tcl b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/xgui/sig_fct_sat_dure_v1_0.tcl
new file mode 100644
index 0000000..525654d
--- /dev/null
+++ b/pb_logique_seq.gen/sources_1/bd/mref/sig_fct_sat_dure/xgui/sig_fct_sat_dure_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.

+proc init_gui { IPINST } {

+  ipgui::add_param $IPINST -name "Component_Name"

+  #Adding Page

+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]

+  ipgui::add_param $IPINST -name "c_ech_u24_max" -parent ${Page_0}

+

+

+}

+

+proc update_PARAM_VALUE.c_ech_u24_max { PARAM_VALUE.c_ech_u24_max } {

+	# Procedure called to update c_ech_u24_max when any of the dependent parameters in the arguments change

+}

+

+proc validate_PARAM_VALUE.c_ech_u24_max { PARAM_VALUE.c_ech_u24_max } {

+	# Procedure called to validate c_ech_u24_max

+	return true

+}

+

+

+proc update_MODELPARAM_VALUE.c_ech_u24_max { MODELPARAM_VALUE.c_ech_u24_max PARAM_VALUE.c_ech_u24_max } {

+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value

+	set_property value [get_property value ${PARAM_VALUE.c_ech_u24_max}] ${MODELPARAM_VALUE.c_ech_u24_max}

+}

+

diff --git a/pb_logique_seq.hw/hw_1/hw.xml b/pb_logique_seq.hw/hw_1/hw.xml
new file mode 100644
index 0000000..0c3115f
--- /dev/null
+++ b/pb_logique_seq.hw/hw_1/hw.xml
@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->

+<!--                                                              -->

+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->

+

+<hwsession version="1" minor="2">

+  <device name="xc7z020_1" gui_info="dashboard1=hw_ila_1[xc7z020_1/hw_ila_1/Waveform=ILA_WAVE_1;xc7z020_1/hw_ila_1/Capture Setup=ILA_CAPTURE_1;xc7z020_1/hw_ila_1/Status=ILA_STATUS_1;xc7z020_1/hw_ila_1/Trigger Setup=ILA_TRIGGER_1;xc7z020_1/hw_ila_1/Settings=ILA_SETTINGS_1;]"/>

+  <ObjectList object_type="hw_device" gui_info="">

+    <Object name="xc7z020_1" gui_info="">

+      <Properties Property="FULL_PROBES.FILE" value="$_project_name_.runs/impl_1/circuit_tr_signal.ltx"/>

+      <Properties Property="PROBES.FILE" value="$_project_name_.runs/impl_1/circuit_tr_signal.ltx"/>

+      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/circuit_tr_signal.bit"/>

+      <Properties Property="SLR.COUNT" value="1"/>

+    </Object>

+  </ObjectList>

+  <ObjectList object_type="hw_ila" gui_info="">

+    <Object name="design_1_i/system_ila_0/U0/ila_lib" gui_info="">

+      <Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>

+      <Properties Property="CORE_REFRESH_RATE_MS" value="500"/>

+    </Object>

+  </ObjectList>

+  <ObjectList object_type="hw_probe" gui_info="">

+    <Object name="design_1_i/system_ila_0/U0/probe1_1[3:0]" gui_info="Trigger Setup=0"/>

+  </ObjectList>

+  <probeset name="hw project" active="false">

+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">

+      <probeOptions Id="DebugProbeParams">

+        <Option Id="CAPTURE_COMPARE_VALUE" value="eq8&apos;hXX"/>

+        <Option Id="COMPARE_VALUE.0" value="eq8&apos;hXX"/>

+        <Option Id="DISPLAY_AS_ENUM" value="1"/>

+        <Option Id="DISPLAY_HINT" value=""/>

+        <Option Id="DISPLAY_RADIX" value="HEX"/>

+        <Option Id="DISPLAY_VISIBILITY" value=""/>

+        <Option Id="HW_ILA" value="hw_ila_1"/>

+        <Option Id="LINK_TO_WAVEFORM" value="1"/>

+        <Option Id="MAP" value="probe0[7:0]"/>

+        <Option Id="NAME.CUSTOM" value=""/>

+        <Option Id="NAME.SELECT" value="Long"/>

+        <Option Id="SOURCE" value="netlist"/>

+        <Option Id="TRIGGER_COMPARE_VALUE" value="eq8&apos;hXX"/>

+        <Option Id="WAVEFORM_STYLE" value="Digital"/>

+      </probeOptions>

+      <nets>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[7]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[6]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[5]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[4]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[3]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[2]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[1]"/>

+        <net name="design_1_i/system_ila_0/U0/probe0_1[0]"/>

+      </nets>

+    </probe>

+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">

+      <probeOptions Id="DebugProbeParams">

+        <Option Id="CAPTURE_COMPARE_VALUE" value="eq4&apos;hX"/>

+        <Option Id="COMPARE_VALUE.0" value="neq4&apos;h0"/>

+        <Option Id="DISPLAY_AS_ENUM" value="1"/>

+        <Option Id="DISPLAY_HINT" value=""/>

+        <Option Id="DISPLAY_RADIX" value="HEX"/>

+        <Option Id="DISPLAY_VISIBILITY" value=""/>

+        <Option Id="HW_ILA" value="hw_ila_1"/>

+        <Option Id="LINK_TO_WAVEFORM" value="1"/>

+        <Option Id="MAP" value="probe1[3:0]"/>

+        <Option Id="NAME.CUSTOM" value="i_btn_1"/>

+        <Option Id="NAME.SELECT" value="Custom"/>

+        <Option Id="SOURCE" value="netlist"/>

+        <Option Id="TRIGGER_COMPARE_VALUE" value="neq4&apos;h0"/>

+        <Option Id="WAVEFORM_STYLE" value="Digital"/>

+      </probeOptions>

+      <nets>

+        <net name="design_1_i/system_ila_0/U0/probe1_1[3]"/>

+        <net name="design_1_i/system_ila_0/U0/probe1_1[2]"/>

+        <net name="design_1_i/system_ila_0/U0/probe1_1[1]"/>

+        <net name="design_1_i/system_ila_0/U0/probe1_1[0]"/>

+      </nets>

+    </probe>

+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">

+      <probeOptions Id="DebugProbeParams">

+        <Option Id="CAPTURE_COMPARE_VALUE" value="eq2&apos;hX"/>

+        <Option Id="COMPARE_VALUE.0" value="eq2&apos;hX"/>

+        <Option Id="DISPLAY_AS_ENUM" value="1"/>

+        <Option Id="DISPLAY_HINT" value=""/>

+        <Option Id="DISPLAY_RADIX" value="HEX"/>

+        <Option Id="DISPLAY_VISIBILITY" value=""/>

+        <Option Id="HW_ILA" value="hw_ila_1"/>

+        <Option Id="LINK_TO_WAVEFORM" value="1"/>

+        <Option Id="MAP" value="probe2[1:0]"/>

+        <Option Id="NAME.CUSTOM" value="module_commande_0_o_selection_fct"/>

+        <Option Id="NAME.SELECT" value="Custom"/>

+        <Option Id="SOURCE" value="netlist"/>

+        <Option Id="TRIGGER_COMPARE_VALUE" value="eq2&apos;hX"/>

+        <Option Id="WAVEFORM_STYLE" value="Digital"/>

+      </probeOptions>

+      <nets>

+        <net name="design_1_i/system_ila_0/U0/probe2_1[1]"/>

+        <net name="design_1_i/system_ila_0/U0/probe2_1[0]"/>

+      </nets>

+    </probe>

+  </probeset>

+</hwsession>

diff --git a/pb_logique_seq.ip_user_files/README.txt b/pb_logique_seq.ip_user_files/README.txt
new file mode 100644
index 0000000..9015e04
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
new file mode 100644
index 0000000..0c61365
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:affhexPmodSSD_v3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_affhexPmodSSD_v3_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_affhexPmodSSD_v3_0_0;
+
+ARCHITECTURE design_1_affhexPmodSSD_v3_0_0_arch OF design_1_affhexPmodSSD_v3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT affhexPmodSSD_v3 IS
+    GENERIC (
+      const_CLK_Hz : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      DA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      JPmod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT affhexPmodSSD_v3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_affhexPmodSSD_v3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : affhexPmodSSD_v3
+    GENERIC MAP (
+      const_CLK_Hz => 100000000
+    )
+    PORT MAP (
+      clk => clk,
+      reset => reset,
+      DA => DA,
+      i_btn => i_btn,
+      JPmod => JPmod
+    );
+END design_1_affhexPmodSSD_v3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
new file mode 100644
index 0000000..b90cd0b
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_1:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_1_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_1_0_0;
+
+ARCHITECTURE design_1_calcul_param_1_0_0_arch OF design_1_calcul_param_1_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_1 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_1;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_1_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_1
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_1_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
new file mode 100644
index 0000000..aeda442
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_2_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_2_0_0;
+
+ARCHITECTURE design_1_calcul_param_2_0_0_arch OF design_1_calcul_param_2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_2 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_2_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_2
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_2_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
new file mode 100644
index 0000000..bc012a0
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd
@@ -0,0 +1,93 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:calcul_param_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_calcul_param_3_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_calcul_param_3_0_0;
+
+ARCHITECTURE design_1_calcul_param_3_0_0_arch OF design_1_calcul_param_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT calcul_param_3 IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_param : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT calcul_param_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_calcul_param_3_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : calcul_param_3
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_ech => i_ech,
+      o_param => o_param
+    );
+END design_1_calcul_param_3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
new file mode 100644
index 0000000..c58480b
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_0;
+
+ARCHITECTURE design_1_compteur_nbits_0_0_arch OF design_1_compteur_nbits_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
new file mode 100644
index 0000000..efc345f
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:compteur_nbits:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_compteur_nbits_0_1 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    reset : IN STD_LOGIC;
+    o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END design_1_compteur_nbits_0_1;
+
+ARCHITECTURE design_1_compteur_nbits_0_1_arch OF design_1_compteur_nbits_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT compteur_nbits IS
+    GENERIC (
+      nbits : INTEGER
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      reset : IN STD_LOGIC;
+      o_val_cpt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+    );
+  END COMPONENT compteur_nbits;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_compteur_nbits_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF reset: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : compteur_nbits
+    GENERIC MAP (
+      nbits => 7
+    )
+    PORT MAP (
+      clk => clk,
+      i_en => i_en,
+      reset => reset,
+      o_val_cpt => o_val_cpt
+    );
+END design_1_compteur_nbits_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
new file mode 100644
index 0000000..9f669ea
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd
@@ -0,0 +1,104 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_cod_i2s_vsb:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_cod_i2s_vsb_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_cod_i2s_vsb_0_0;
+
+ARCHITECTURE design_1_mef_cod_i2s_vsb_0_0_arch OF design_1_mef_cod_i2s_vsb_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_cod_i2s_vsb IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_cod_i2s_vsb;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_cod_i2s_vsb_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_cod_i2s_vsb
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_cod_i2s_vsb_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
new file mode 100644
index 0000000..63454ae
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd
@@ -0,0 +1,107 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mef_decod_i2s_v1b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mef_decod_i2s_v1b_0_0 IS
+  PORT (
+    i_bclk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_lrc : IN STD_LOGIC;
+    i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    o_bit_enable : OUT STD_LOGIC;
+    o_load_left : OUT STD_LOGIC;
+    o_load_right : OUT STD_LOGIC;
+    o_str_dat : OUT STD_LOGIC;
+    o_cpt_bit_reset : OUT STD_LOGIC
+  );
+END design_1_mef_decod_i2s_v1b_0_0;
+
+ARCHITECTURE design_1_mef_decod_i2s_v1b_0_0_arch OF design_1_mef_decod_i2s_v1b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mef_decod_i2s_v1b IS
+    PORT (
+      i_bclk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_lrc : IN STD_LOGIC;
+      i_cpt_bits : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      o_bit_enable : OUT STD_LOGIC;
+      o_load_left : OUT STD_LOGIC;
+      o_load_right : OUT STD_LOGIC;
+      o_str_dat : OUT STD_LOGIC;
+      o_cpt_bit_reset : OUT STD_LOGIC
+    );
+  END COMPONENT mef_decod_i2s_v1b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mef_decod_i2s_v1b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_cpt_bit_reset: SIGNAL IS "XIL_INTERFACENAME o_cpt_bit_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_cpt_bit_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_cpt_bit_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+BEGIN
+  U0 : mef_decod_i2s_v1b
+    PORT MAP (
+      i_bclk => i_bclk,
+      i_reset => i_reset,
+      i_lrc => i_lrc,
+      i_cpt_bits => i_cpt_bits,
+      o_bit_enable => o_bit_enable,
+      o_load_left => o_load_left,
+      o_load_right => o_load_right,
+      o_str_dat => o_str_dat,
+      o_cpt_bit_reset => o_cpt_bit_reset
+    );
+END design_1_mef_decod_i2s_v1b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
new file mode 100644
index 0000000..643d8ee
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd
@@ -0,0 +1,109 @@
+-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:module_commande:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_module_commande_0_0 IS
+  PORT (
+    clk : IN STD_LOGIC;
+    o_reset : OUT STD_LOGIC;
+    i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+  );
+END design_1_module_commande_0_0;
+
+ARCHITECTURE design_1_module_commande_0_0_arch OF design_1_module_commande_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT module_commande IS
+    GENERIC (
+      nbtn : INTEGER;
+      mode_simulation : STD_LOGIC
+    );
+    PORT (
+      clk : IN STD_LOGIC;
+      o_reset : OUT STD_LOGIC;
+      i_btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      i_sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_btn_cd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      o_selection_fct : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      o_selection_par : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+  END COMPONENT module_commande;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_module_commande_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF o_reset: SIGNAL IS "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF o_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 o_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
+BEGIN
+  U0 : module_commande
+    GENERIC MAP (
+      nbtn => 4,
+      mode_simulation => '0'
+    )
+    PORT MAP (
+      clk => clk,
+      o_reset => o_reset,
+      i_btn => i_btn,
+      i_sw => i_sw,
+      o_btn_cd => o_btn_cd,
+      o_selection_fct => o_selection_fct,
+      o_selection_par => o_selection_par
+    );
+END design_1_module_commande_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
new file mode 100644
index 0000000..ffe2904
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd
@@ -0,0 +1,92 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux2:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux2_0_0 IS
+  PORT (
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux2_0_0;
+
+ARCHITECTURE design_1_mux2_0_0_arch OF design_1_mux2_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux2_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux2 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux2;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux2_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux2
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      sel => sel,
+      input1 => input1,
+      input2 => input2,
+      output0 => output0
+    );
+END design_1_mux2_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
new file mode 100644
index 0000000..ae6ac28
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_0 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_mux4_0_0;
+
+ARCHITECTURE design_1_mux4_0_0_arch OF design_1_mux4_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 24
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
new file mode 100644
index 0000000..d30d1e5
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd
@@ -0,0 +1,98 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:mux4:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_mux4_0_1 IS
+  PORT (
+    input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END design_1_mux4_0_1;
+
+ARCHITECTURE design_1_mux4_0_1_arch OF design_1_mux4_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mux4_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT mux4 IS
+    GENERIC (
+      input_length : INTEGER
+    );
+    PORT (
+      input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      output0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+    );
+  END COMPONENT mux4;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_mux4_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : mux4
+    GENERIC MAP (
+      input_length => 8
+    )
+    PORT MAP (
+      input0 => input0,
+      input1 => input1,
+      input2 => input2,
+      input3 => input3,
+      sel => sel,
+      output0 => output0
+    );
+END design_1_mux4_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
new file mode 100644
index 0000000..4ef9d64
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_0;
+
+ARCHITECTURE design_1_reg_24b_0_0_arch OF design_1_reg_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
new file mode 100644
index 0000000..3883a48
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_24b_0_1 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_24b_0_1;
+
+ARCHITECTURE design_1_reg_24b_0_1_arch OF design_1_reg_24b_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_24b_0_1_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_en => i_en,
+      i_dat => i_dat,
+      o_dat => o_dat
+    );
+END design_1_reg_24b_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
new file mode 100644
index 0000000..2dbb12a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_0_0_arch OF design_1_reg_dec_24b_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
new file mode 100644
index 0000000..c8a9b85
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:reg_dec_24b_fd:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_reg_dec_24b_fd_0_0 IS
+  PORT (
+    i_clk : IN STD_LOGIC;
+    i_reset : IN STD_LOGIC;
+    i_load : IN STD_LOGIC;
+    i_en : IN STD_LOGIC;
+    i_dat_bit : IN STD_LOGIC;
+    i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_reg_dec_24b_fd_0_0;
+
+ARCHITECTURE design_1_reg_dec_24b_fd_0_0_arch OF design_1_reg_dec_24b_fd_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT reg_dec_24b_fd IS
+    PORT (
+      i_clk : IN STD_LOGIC;
+      i_reset : IN STD_LOGIC;
+      i_load : IN STD_LOGIC;
+      i_en : IN STD_LOGIC;
+      i_dat_bit : IN STD_LOGIC;
+      i_dat_load : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_dat : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT reg_dec_24b_fd;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_reg_dec_24b_fd_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_reset: SIGNAL IS "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 i_reset RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF i_clk: SIGNAL IS "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk_100MHz, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF i_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_clk CLK";
+BEGIN
+  U0 : reg_dec_24b_fd
+    PORT MAP (
+      i_clk => i_clk,
+      i_reset => i_reset,
+      i_load => i_load,
+      i_en => i_en,
+      i_dat_bit => i_dat_bit,
+      i_dat_load => i_dat_load,
+      o_dat => o_dat
+    );
+END design_1_reg_dec_24b_fd_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
new file mode 100644
index 0000000..3a84972
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd
@@ -0,0 +1,80 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_3:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_3_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_3_0_0;
+
+ARCHITECTURE design_1_sig_fct_3_0_0_arch OF design_1_sig_fct_3_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_3 IS
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_3;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_3_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_3
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_3_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
new file mode 100644
index 0000000..27c63d5
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_0 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_0;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_0_arch OF design_1_sig_fct_sat_dure_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_0_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"7FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_0_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
new file mode 100644
index 0000000..b557a37
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd
@@ -0,0 +1,86 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:sig_fct_sat_dure:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY design_1_sig_fct_sat_dure_0_1 IS
+  PORT (
+    i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+    o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END design_1_sig_fct_sat_dure_0_1;
+
+ARCHITECTURE design_1_sig_fct_sat_dure_0_1_arch OF design_1_sig_fct_sat_dure_0_1 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "yes";
+  COMPONENT sig_fct_sat_dure IS
+    GENERIC (
+      c_ech_u24_max : UNSIGNED(23 DOWNTO 0)
+    );
+    PORT (
+      i_ech : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+      o_ech_fct : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+    );
+  END COMPONENT sig_fct_sat_dure;
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_sig_fct_sat_dure_0_1_arch: ARCHITECTURE IS "module_ref";
+BEGIN
+  U0 : sig_fct_sat_dure
+    GENERIC MAP (
+      c_ech_u24_max => X"1FFFFF"
+    )
+    PORT MAP (
+      i_ech => i_ech,
+      o_ech_fct => o_ech_fct
+    );
+END design_1_sig_fct_sat_dure_0_1_arch;
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
new file mode 100644
index 0000000..c3f6299
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v
@@ -0,0 +1,74 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_util_vector_logic_0_0 (
+  Op1,
+  Op2,
+  Res
+);
+
+input wire [0 : 0] Op1;
+input wire [0 : 0] Op2;
+output wire [0 : 0] Res;
+
+  util_vector_logic_v2_0_1_util_vector_logic #(
+    .C_OPERATION("or"),
+    .C_SIZE(1)
+  ) inst (
+    .Op1(Op1),
+    .Op2(Op2),
+    .Res(Res)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
new file mode 100644
index 0000000..25b5d97
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v
@@ -0,0 +1,328 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconcat:2.1
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconcat_0_0 (
+  In0,
+  In1,
+  dout
+);
+
+input wire [0 : 0] In0;
+input wire [0 : 0] In1;
+output wire [1 : 0] dout;
+
+  xlconcat_v2_1_4_xlconcat #(
+    .IN0_WIDTH(1),
+    .IN1_WIDTH(1),
+    .IN2_WIDTH(1),
+    .IN3_WIDTH(1),
+    .IN4_WIDTH(1),
+    .IN5_WIDTH(1),
+    .IN6_WIDTH(1),
+    .IN7_WIDTH(1),
+    .IN8_WIDTH(1),
+    .IN9_WIDTH(1),
+    .IN10_WIDTH(1),
+    .IN11_WIDTH(1),
+    .IN12_WIDTH(1),
+    .IN13_WIDTH(1),
+    .IN14_WIDTH(1),
+    .IN15_WIDTH(1),
+    .IN16_WIDTH(1),
+    .IN17_WIDTH(1),
+    .IN18_WIDTH(1),
+    .IN19_WIDTH(1),
+    .IN20_WIDTH(1),
+    .IN21_WIDTH(1),
+    .IN22_WIDTH(1),
+    .IN23_WIDTH(1),
+    .IN24_WIDTH(1),
+    .IN25_WIDTH(1),
+    .IN26_WIDTH(1),
+    .IN27_WIDTH(1),
+    .IN28_WIDTH(1),
+    .IN29_WIDTH(1),
+    .IN30_WIDTH(1),
+    .IN31_WIDTH(1),
+    .IN32_WIDTH(1),
+    .IN33_WIDTH(1),
+    .IN34_WIDTH(1),
+    .IN35_WIDTH(1),
+    .IN36_WIDTH(1),
+    .IN37_WIDTH(1),
+    .IN38_WIDTH(1),
+    .IN39_WIDTH(1),
+    .IN40_WIDTH(1),
+    .IN41_WIDTH(1),
+    .IN42_WIDTH(1),
+    .IN43_WIDTH(1),
+    .IN44_WIDTH(1),
+    .IN45_WIDTH(1),
+    .IN46_WIDTH(1),
+    .IN47_WIDTH(1),
+    .IN48_WIDTH(1),
+    .IN49_WIDTH(1),
+    .IN50_WIDTH(1),
+    .IN51_WIDTH(1),
+    .IN52_WIDTH(1),
+    .IN53_WIDTH(1),
+    .IN54_WIDTH(1),
+    .IN55_WIDTH(1),
+    .IN56_WIDTH(1),
+    .IN57_WIDTH(1),
+    .IN58_WIDTH(1),
+    .IN59_WIDTH(1),
+    .IN60_WIDTH(1),
+    .IN61_WIDTH(1),
+    .IN62_WIDTH(1),
+    .IN63_WIDTH(1),
+    .IN64_WIDTH(1),
+    .IN65_WIDTH(1),
+    .IN66_WIDTH(1),
+    .IN67_WIDTH(1),
+    .IN68_WIDTH(1),
+    .IN69_WIDTH(1),
+    .IN70_WIDTH(1),
+    .IN71_WIDTH(1),
+    .IN72_WIDTH(1),
+    .IN73_WIDTH(1),
+    .IN74_WIDTH(1),
+    .IN75_WIDTH(1),
+    .IN76_WIDTH(1),
+    .IN77_WIDTH(1),
+    .IN78_WIDTH(1),
+    .IN79_WIDTH(1),
+    .IN80_WIDTH(1),
+    .IN81_WIDTH(1),
+    .IN82_WIDTH(1),
+    .IN83_WIDTH(1),
+    .IN84_WIDTH(1),
+    .IN85_WIDTH(1),
+    .IN86_WIDTH(1),
+    .IN87_WIDTH(1),
+    .IN88_WIDTH(1),
+    .IN89_WIDTH(1),
+    .IN90_WIDTH(1),
+    .IN91_WIDTH(1),
+    .IN92_WIDTH(1),
+    .IN93_WIDTH(1),
+    .IN94_WIDTH(1),
+    .IN95_WIDTH(1),
+    .IN96_WIDTH(1),
+    .IN97_WIDTH(1),
+    .IN98_WIDTH(1),
+    .IN99_WIDTH(1),
+    .IN100_WIDTH(1),
+    .IN101_WIDTH(1),
+    .IN102_WIDTH(1),
+    .IN103_WIDTH(1),
+    .IN104_WIDTH(1),
+    .IN105_WIDTH(1),
+    .IN106_WIDTH(1),
+    .IN107_WIDTH(1),
+    .IN108_WIDTH(1),
+    .IN109_WIDTH(1),
+    .IN110_WIDTH(1),
+    .IN111_WIDTH(1),
+    .IN112_WIDTH(1),
+    .IN113_WIDTH(1),
+    .IN114_WIDTH(1),
+    .IN115_WIDTH(1),
+    .IN116_WIDTH(1),
+    .IN117_WIDTH(1),
+    .IN118_WIDTH(1),
+    .IN119_WIDTH(1),
+    .IN120_WIDTH(1),
+    .IN121_WIDTH(1),
+    .IN122_WIDTH(1),
+    .IN123_WIDTH(1),
+    .IN124_WIDTH(1),
+    .IN125_WIDTH(1),
+    .IN126_WIDTH(1),
+    .IN127_WIDTH(1),
+    .dout_width(2),
+    .NUM_PORTS(2)
+  ) inst (
+    .In0(In0),
+    .In1(In1),
+    .In2(1'B0),
+    .In3(1'B0),
+    .In4(1'B0),
+    .In5(1'B0),
+    .In6(1'B0),
+    .In7(1'B0),
+    .In8(1'B0),
+    .In9(1'B0),
+    .In10(1'B0),
+    .In11(1'B0),
+    .In12(1'B0),
+    .In13(1'B0),
+    .In14(1'B0),
+    .In15(1'B0),
+    .In16(1'B0),
+    .In17(1'B0),
+    .In18(1'B0),
+    .In19(1'B0),
+    .In20(1'B0),
+    .In21(1'B0),
+    .In22(1'B0),
+    .In23(1'B0),
+    .In24(1'B0),
+    .In25(1'B0),
+    .In26(1'B0),
+    .In27(1'B0),
+    .In28(1'B0),
+    .In29(1'B0),
+    .In30(1'B0),
+    .In31(1'B0),
+    .In32(1'B0),
+    .In33(1'B0),
+    .In34(1'B0),
+    .In35(1'B0),
+    .In36(1'B0),
+    .In37(1'B0),
+    .In38(1'B0),
+    .In39(1'B0),
+    .In40(1'B0),
+    .In41(1'B0),
+    .In42(1'B0),
+    .In43(1'B0),
+    .In44(1'B0),
+    .In45(1'B0),
+    .In46(1'B0),
+    .In47(1'B0),
+    .In48(1'B0),
+    .In49(1'B0),
+    .In50(1'B0),
+    .In51(1'B0),
+    .In52(1'B0),
+    .In53(1'B0),
+    .In54(1'B0),
+    .In55(1'B0),
+    .In56(1'B0),
+    .In57(1'B0),
+    .In58(1'B0),
+    .In59(1'B0),
+    .In60(1'B0),
+    .In61(1'B0),
+    .In62(1'B0),
+    .In63(1'B0),
+    .In64(1'B0),
+    .In65(1'B0),
+    .In66(1'B0),
+    .In67(1'B0),
+    .In68(1'B0),
+    .In69(1'B0),
+    .In70(1'B0),
+    .In71(1'B0),
+    .In72(1'B0),
+    .In73(1'B0),
+    .In74(1'B0),
+    .In75(1'B0),
+    .In76(1'B0),
+    .In77(1'B0),
+    .In78(1'B0),
+    .In79(1'B0),
+    .In80(1'B0),
+    .In81(1'B0),
+    .In82(1'B0),
+    .In83(1'B0),
+    .In84(1'B0),
+    .In85(1'B0),
+    .In86(1'B0),
+    .In87(1'B0),
+    .In88(1'B0),
+    .In89(1'B0),
+    .In90(1'B0),
+    .In91(1'B0),
+    .In92(1'B0),
+    .In93(1'B0),
+    .In94(1'B0),
+    .In95(1'B0),
+    .In96(1'B0),
+    .In97(1'B0),
+    .In98(1'B0),
+    .In99(1'B0),
+    .In100(1'B0),
+    .In101(1'B0),
+    .In102(1'B0),
+    .In103(1'B0),
+    .In104(1'B0),
+    .In105(1'B0),
+    .In106(1'B0),
+    .In107(1'B0),
+    .In108(1'B0),
+    .In109(1'B0),
+    .In110(1'B0),
+    .In111(1'B0),
+    .In112(1'B0),
+    .In113(1'B0),
+    .In114(1'B0),
+    .In115(1'B0),
+    .In116(1'B0),
+    .In117(1'B0),
+    .In118(1'B0),
+    .In119(1'B0),
+    .In120(1'B0),
+    .In121(1'B0),
+    .In122(1'B0),
+    .In123(1'B0),
+    .In124(1'B0),
+    .In125(1'B0),
+    .In126(1'B0),
+    .In127(1'B0),
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
new file mode 100644
index 0000000..a112873
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_0 (
+  dout
+);
+
+output wire [7 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(8),
+    .CONST_VAL(8'H00)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
new file mode 100644
index 0000000..31c4f41
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_1 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
new file mode 100644
index 0000000..5011eda
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_2 (
+  dout
+);
+
+output wire [0 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(1),
+    .CONST_VAL(1'H1)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
new file mode 100644
index 0000000..65ddfe3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v
@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 7
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlconstant_0_3 (
+  dout
+);
+
+output wire [23 : 0] dout;
+
+  xlconstant_v1_1_7_xlconstant #(
+    .CONST_WIDTH(24),
+    .CONST_VAL(24'H000001)
+  ) inst (
+    .dout(dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
new file mode 100644
index 0000000..c5f22b1
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v
@@ -0,0 +1,72 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlslice:1.0
+// IP Revision: 2
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_xlslice_0_0 (
+  Din,
+  Dout
+);
+
+input wire [23 : 0] Din;
+output wire [0 : 0] Dout;
+
+  xlslice_v1_0_2_xlslice #(
+    .DIN_WIDTH(24),
+    .DIN_FROM(23),
+    .DIN_TO(23)
+  ) inst (
+    .Din(Din),
+    .Dout(Dout)
+  );
+endmodule
diff --git a/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd b/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd
new file mode 100644
index 0000000..4fbeb11
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/bd/design_1/sim/design_1.vhd
@@ -0,0 +1,581 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Jan 16 11:48:36 2024
+--Host        : gegi-3014-bmwin running 64-bit major release  (build 9200)
+--Command     : generate_target design_1.bd
+--Design      : design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M1_decodeur_i2s_imp_17RYJKZ is
+  port (
+    clk : in STD_LOGIC;
+    i_data : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat_left : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat_right : out STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_str_dat : out STD_LOGIC
+  );
+end M1_decodeur_i2s_imp_17RYJKZ;
+
+architecture STRUCTURE of M1_decodeur_i2s_imp_17RYJKZ is
+  component design_1_compteur_nbits_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_0;
+  component design_1_mef_decod_i2s_v1b_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_str_dat : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_decod_i2s_v1b_0_0;
+  component design_1_reg_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_0;
+  component design_1_reg_24b_0_1 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_24b_0_1;
+  component design_1_reg_dec_24b_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_0_0;
+  component design_1_xlconstant_0_2 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_2;
+  component design_1_xlconstant_0_3 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_xlconstant_0_3;
+  signal clk_1 : STD_LOGIC;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_bit_enable : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_left : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_load_right : STD_LOGIC;
+  signal mef_decod_i2s_v1b_0_o_str_dat : STD_LOGIC;
+  signal reg_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_24b_1_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
+begin
+  clk_1 <= clk;
+  i_data_1 <= i_data;
+  i_lrc_1 <= i_lrc;
+  i_reset_1 <= i_reset;
+  o_dat_left(23 downto 0) <= reg_24b_1_o_dat(23 downto 0);
+  o_dat_right(23 downto 0) <= reg_24b_0_o_dat(23 downto 0);
+  o_str_dat <= mef_decod_i2s_v1b_0_o_str_dat;
+MEF_decodeur_i2s: component design_1_mef_decod_i2s_v1b_0_0
+     port map (
+      i_bclk => clk_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_bit_enable => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_cpt_bit_reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset,
+      o_load_left => mef_decod_i2s_v1b_0_o_load_left,
+      o_load_right => mef_decod_i2s_v1b_0_o_load_right,
+      o_str_dat => mef_decod_i2s_v1b_0_o_str_dat
+    );
+compteur_7bits: component design_1_compteur_nbits_0_0
+     port map (
+      clk => clk_1,
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_decod_i2s_v1b_0_o_cpt_bit_reset
+    );
+registre_24bits_droite: component design_1_reg_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_right,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_0_o_dat(23 downto 0)
+    );
+registre_24bits_gauche: component design_1_reg_24b_0_1
+     port map (
+      i_clk => clk_1,
+      i_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_load_left,
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_24b_1_o_dat(23 downto 0)
+    );
+registre_decalage_24bits: component design_1_reg_dec_24b_0_0
+     port map (
+      i_clk => clk_1,
+      i_dat_bit => i_data_1,
+      i_dat_load(23 downto 0) => xlconstant_1_dout(23 downto 0),
+      i_en => mef_decod_i2s_v1b_0_o_bit_enable,
+      i_load => xlconstant_0_dout(0),
+      i_reset => i_reset_1,
+      o_dat(23 downto 0) => reg_dec_24b_0_o_dat(23 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_2
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlconstant_1: component design_1_xlconstant_0_3
+     port map (
+      dout(23 downto 0) => xlconstant_1_dout(23 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity M9_codeur_i2s_imp_1VJCTGL is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_dat_left : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_dat_right : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    o_dat : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end M9_codeur_i2s_imp_1VJCTGL;
+
+architecture STRUCTURE of M9_codeur_i2s_imp_1VJCTGL is
+  component design_1_compteur_nbits_0_1 is
+  port (
+    clk : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    o_val_cpt : out STD_LOGIC_VECTOR ( 6 downto 0 )
+  );
+  end component design_1_compteur_nbits_0_1;
+  component design_1_mef_cod_i2s_vsb_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_cpt_bits : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    o_bit_enable : out STD_LOGIC;
+    o_load_left : out STD_LOGIC;
+    o_load_right : out STD_LOGIC;
+    o_cpt_bit_reset : out STD_LOGIC
+  );
+  end component design_1_mef_cod_i2s_vsb_0_0;
+  component design_1_mux2_0_0 is
+  port (
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux2_0_0;
+  component design_1_reg_dec_24b_fd_0_0 is
+  port (
+    i_clk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_load : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_dat_bit : in STD_LOGIC;
+    i_dat_load : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_dat : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_reg_dec_24b_fd_0_0;
+  component design_1_util_vector_logic_0_0 is
+  port (
+    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_util_vector_logic_0_0;
+  component design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_xlconcat_0_0;
+  component design_1_xlconstant_0_1 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlconstant_0_1;
+  component design_1_xlslice_0_0 is
+  port (
+    Din : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component design_1_xlslice_0_0;
+  signal compteur_nbits_0_o_val_cpt : STD_LOGIC_VECTOR ( 6 downto 0 );
+  signal i_bclk_0_1 : STD_LOGIC;
+  signal i_lrc_0_1 : STD_LOGIC;
+  signal i_reset_0_1 : STD_LOGIC;
+  signal input1_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal input2_0_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal mef_cod_i2s_vsb_0_o_bit_enable : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_cpt_bit_reset : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_left : STD_LOGIC;
+  signal mef_cod_i2s_vsb_0_o_load_right : STD_LOGIC;
+  signal mux2_0_output : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal reg_dec_24b_fd_0_o_dat : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  i_bclk_0_1 <= i_bclk;
+  i_lrc_0_1 <= i_lrc;
+  i_reset_0_1 <= i_reset;
+  input1_0_1(23 downto 0) <= i_dat_left(23 downto 0);
+  input2_0_1(23 downto 0) <= i_dat_right(23 downto 0);
+  o_dat(0) <= xlslice_0_Dout(0);
+compteur_nbits_0: component design_1_compteur_nbits_0_1
+     port map (
+      clk => i_bclk_0_1,
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_val_cpt(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset
+    );
+mef_cod_i2s_vsb_0: component design_1_mef_cod_i2s_vsb_0_0
+     port map (
+      i_bclk => i_bclk_0_1,
+      i_cpt_bits(6 downto 0) => compteur_nbits_0_o_val_cpt(6 downto 0),
+      i_lrc => i_lrc_0_1,
+      i_reset => i_reset_0_1,
+      o_bit_enable => mef_cod_i2s_vsb_0_o_bit_enable,
+      o_cpt_bit_reset => mef_cod_i2s_vsb_0_o_cpt_bit_reset,
+      o_load_left => mef_cod_i2s_vsb_0_o_load_left,
+      o_load_right => mef_cod_i2s_vsb_0_o_load_right
+    );
+mux2_0: component design_1_mux2_0_0
+     port map (
+      input1(23 downto 0) => input1_0_1(23 downto 0),
+      input2(23 downto 0) => input2_0_1(23 downto 0),
+      output0(23 downto 0) => mux2_0_output(23 downto 0),
+      sel(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+reg_dec_24b_fd_0: component design_1_reg_dec_24b_fd_0_0
+     port map (
+      i_clk => i_bclk_0_1,
+      i_dat_bit => xlconstant_0_dout(0),
+      i_dat_load(23 downto 0) => mux2_0_output(23 downto 0),
+      i_en => mef_cod_i2s_vsb_0_o_bit_enable,
+      i_load => util_vector_logic_0_Res(0),
+      i_reset => i_reset_0_1,
+      o_dat(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0)
+    );
+util_vector_logic_0: component design_1_util_vector_logic_0_0
+     port map (
+      Op1(0) => mef_cod_i2s_vsb_0_o_load_left,
+      Op2(0) => mef_cod_i2s_vsb_0_o_load_right,
+      Res(0) => util_vector_logic_0_Res(0)
+    );
+xlconcat_0: component design_1_xlconcat_0_0
+     port map (
+      In0(0) => mef_cod_i2s_vsb_0_o_load_left,
+      In1(0) => mef_cod_i2s_vsb_0_o_load_right,
+      dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
+    );
+xlconstant_0: component design_1_xlconstant_0_1
+     port map (
+      dout(0) => xlconstant_0_dout(0)
+    );
+xlslice_0: component design_1_xlslice_0_0
+     port map (
+      Din(23 downto 0) => reg_dec_24b_fd_0_o_dat(23 downto 0),
+      Dout(0) => xlslice_0_Dout(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- Modules à modifier:
+  -- MEF_decodeur_i2s (dans M1_decodeur_i2s)
+  -- M5_parametre_1
+  -- M6_parametre_2
+  -- M8_commande
+  -- Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+  -- et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+  entity design_1 is
+  port (
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_lrc : in STD_LOGIC;
+    i_recdat : in STD_LOGIC;
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=28,numReposBlks=26,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=19,numPkgbdBlks=0,bdsource=USER,""""""""""""""""""""""""""""""""""""""""""""""""""""da_clkrst_cnt""""""""""""""""""""""""""""""""""""""""""""""""""""=1,synth_mode=OOC_per_IP}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
+end design_1;
+
+architecture STRUCTURE of design_1 is
+  component design_1_affhexPmodSSD_v3_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    DA : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_affhexPmodSSD_v3_0_0;
+  component design_1_calcul_param_1_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_1_0_0;
+  component design_1_calcul_param_2_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_2_0_0;
+  component design_1_calcul_param_3_0_0 is
+  port (
+    i_bclk : in STD_LOGIC;
+    i_reset : in STD_LOGIC;
+    i_en : in STD_LOGIC;
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_calcul_param_3_0_0;
+  component design_1_mux4_0_0 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_mux4_0_0;
+  component design_1_mux4_0_1 is
+  port (
+    input0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    input3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    sel : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    output0 : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_mux4_0_1;
+  component design_1_sig_fct_3_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_3_0_0;
+  component design_1_sig_fct_sat_dure_0_0 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_0;
+  component design_1_sig_fct_sat_dure_0_1 is
+  port (
+    i_ech : in STD_LOGIC_VECTOR ( 23 downto 0 );
+    o_ech_fct : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+  end component design_1_sig_fct_sat_dure_0_1;
+  component design_1_xlconstant_0_0 is
+  port (
+    dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component design_1_xlconstant_0_0;
+  component design_1_module_commande_0_0 is
+  port (
+    clk : in STD_LOGIC;
+    o_reset : out STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_btn_cd : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    o_selection_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_selection_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1_module_commande_0_0;
+  signal M10_conversion_affichage_JPmod : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal M8_commande_o_btn_cd : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal M8_commande_o_selection_par : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal M9_codeur_i2s_o_dat : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal calcul_param_1_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_2_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal calcul_param_3_0_o_param : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal clk_1 : STD_LOGIC;
+  signal decodeur_i2s_o_dat_right : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal decodeur_i2s_o_str_dat : STD_LOGIC;
+  signal i_btn_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal i_dat_left_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_dat_right_1 : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal i_data_1 : STD_LOGIC;
+  signal i_lrc_1 : STD_LOGIC;
+  signal i_reset_1 : STD_LOGIC;
+  signal i_sw_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal module_commande_0_o_selection_fct : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal mux4_1_output : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal sig_fct_3_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_0_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal sig_fct_sat_dure_1_o_ech_fct : STD_LOGIC_VECTOR ( 23 downto 0 );
+  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_100MHz : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_100MHZ CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_100MHz : signal is "XIL_INTERFACENAME CLK.CLK_100MHZ, CLK_DOMAIN design_1_clk_100MHz, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
+begin
+  JPmod(7 downto 0) <= M10_conversion_affichage_JPmod(7 downto 0);
+  clk_1 <= clk_100MHz;
+  i_btn_1(3 downto 0) <= i_btn(3 downto 0);
+  i_data_1 <= i_recdat;
+  i_lrc_1 <= i_lrc;
+  i_sw_1(3 downto 0) <= i_sw(3 downto 0);
+  o_param(7 downto 0) <= mux4_1_output(7 downto 0);
+  o_pbdat(0) <= M9_codeur_i2s_o_dat(0);
+  o_sel_fct(1 downto 0) <= module_commande_0_o_selection_fct(1 downto 0);
+  o_sel_par(1 downto 0) <= M8_commande_o_selection_par(1 downto 0);
+M10_conversion_affichage: component design_1_affhexPmodSSD_v3_0_0
+     port map (
+      DA(7 downto 0) => mux4_1_output(7 downto 0),
+      JPmod(7 downto 0) => M10_conversion_affichage_JPmod(7 downto 0),
+      clk => clk_1,
+      i_btn(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      reset => i_reset_1
+    );
+M1_decodeur_i2s: entity work.M1_decodeur_i2s_imp_17RYJKZ
+     port map (
+      clk => clk_1,
+      i_data => i_data_1,
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      o_dat_right(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_str_dat => decodeur_i2s_o_str_dat
+    );
+M2_fonction_distortion_dure1: component design_1_sig_fct_sat_dure_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0)
+    );
+M3_fonction_distorsion_dure2: component design_1_sig_fct_sat_dure_0_1
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0)
+    );
+M4_fonction3: component design_1_sig_fct_3_0_0
+     port map (
+      i_ech(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      o_ech_fct(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0)
+    );
+M5_parametre_1: component design_1_calcul_param_1_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_1_0_o_param(7 downto 0)
+    );
+M6_parametre_2: component design_1_calcul_param_2_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_2_0_o_param(7 downto 0)
+    );
+M7_parametre_3: component design_1_calcul_param_3_0_0
+     port map (
+      i_bclk => clk_1,
+      i_ech(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_en => decodeur_i2s_o_str_dat,
+      i_reset => i_reset_1,
+      o_param(7 downto 0) => calcul_param_3_0_o_param(7 downto 0)
+    );
+M8_commande: component design_1_module_commande_0_0
+     port map (
+      clk => clk_1,
+      i_btn(3 downto 0) => i_btn_1(3 downto 0),
+      i_sw(3 downto 0) => i_sw_1(3 downto 0),
+      o_btn_cd(3 downto 0) => M8_commande_o_btn_cd(3 downto 0),
+      o_reset => i_reset_1,
+      o_selection_fct(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0),
+      o_selection_par(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+M9_codeur_i2s: entity work.M9_codeur_i2s_imp_1VJCTGL
+     port map (
+      i_bclk => clk_1,
+      i_dat_left(23 downto 0) => i_dat_left_1(23 downto 0),
+      i_dat_right(23 downto 0) => i_dat_right_1(23 downto 0),
+      i_lrc => i_lrc_1,
+      i_reset => i_reset_1,
+      o_dat(0) => M9_codeur_i2s_o_dat(0)
+    );
+Multiplexeur_choix_fonction: component design_1_mux4_0_0
+     port map (
+      input0(23 downto 0) => decodeur_i2s_o_dat_right(23 downto 0),
+      input1(23 downto 0) => sig_fct_sat_dure_0_o_ech_fct(23 downto 0),
+      input2(23 downto 0) => sig_fct_sat_dure_1_o_ech_fct(23 downto 0),
+      input3(23 downto 0) => sig_fct_3_0_o_ech_fct(23 downto 0),
+      output0(23 downto 0) => i_dat_right_1(23 downto 0),
+      sel(1 downto 0) => module_commande_0_o_selection_fct(1 downto 0)
+    );
+Multiplexeur_choix_parametre: component design_1_mux4_0_1
+     port map (
+      input0(7 downto 0) => xlconstant_0_dout(7 downto 0),
+      input1(7 downto 0) => calcul_param_1_0_o_param(7 downto 0),
+      input2(7 downto 0) => calcul_param_2_0_o_param(7 downto 0),
+      input3(7 downto 0) => calcul_param_3_0_o_param(7 downto 0),
+      output0(7 downto 0) => mux4_1_output(7 downto 0),
+      sel(1 downto 0) => M8_commande_o_selection_par(1 downto 0)
+    );
+parametre_0: component design_1_xlconstant_0_0
+     port map (
+      dout(7 downto 0) => xlconstant_0_dout(7 downto 0)
+    );
+end STRUCTURE;
diff --git a/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/mem_init_files/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/mem_init_files/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/mem_init_files/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/mem_init_files/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/README.txt
new file mode 100644
index 0000000..3bf1c4a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/README.txt
@@ -0,0 +1,83 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required

+#             to simulate the design for a simulator, the directory structure

+#             and the generated exported files.

+#

+################################################################################

+

+1. Simulate Design

+

+To simulate design, cd to the simulator directory and execute the script.

+

+For example:-

+

+% cd questa

+% ./top.sh

+

+The export simulation flow requires the Xilinx pre-compiled simulation library

+components for the target simulator. These components are referred using the

+'-lib_map_path' switch. If this switch is specified, then the export simulation

+will automatically set this library path in the generated script and update,

+copy the simulator setup file(s) in the exported directory.

+

+If '-lib_map_path' is not specified, then the pre-compiled simulation library

+information will not be included in the exported scripts and that may cause

+simulation errors when running this script. Alternatively, you can provide the

+library information using this switch while executing the generated script.

+

+For example:-

+

+% ./top.sh -lib_map_path /design/questa/clibs

+

+Please refer to the generated script header 'Prerequisite' section for more details.

+

+2. Directory Structure

+

+By default, if the -directory switch is not specified, export_simulation will

+create the following directory structure:-

+

+<current_working_directory>/export_sim/<simulator>

+

+For example, if the current working directory is /tmp/test, export_simulation

+will create the following directory path:-

+

+/tmp/test/export_sim/questa

+

+If -directory switch is specified, export_simulation will create a simulator

+sub-directory under the specified directory path.

+

+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'

+command will create the following directory:-

+

+/tmp/test/my_test_area/func_sim/questa

+

+By default, if -simulator is not specified, export_simulation will create a

+simulator sub-directory for each simulator and export the files for each simulator

+in this sub-directory respectively.

+

+IMPORTANT: Please note that the simulation library path must be specified manually

+in the generated script for the respective simulator. Please refer to the generated

+script header 'Prerequisite' section for more details.

+

+3. Exported script and files

+

+Export simulation will create the driver shell script, setup files and copy the

+design sources in the output directory path.

+

+By default, when the -script_name switch is not specified, export_simulation will

+create the following script name:-

+

+<simulation_top>.sh  (Unix)

+When exporting the files for an IP using the -of_objects switch, export_simulation

+will create the following script name:-

+

+<ip-name>.sh  (Unix)

+Export simulation will create the setup files for the target simulator specified

+with the -simulator switch.

+

+For example, if the target simulator is "ies", export_simulation will create the

+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'

+file.

+

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/activehdl/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/README.txt
new file mode 100644
index 0000000..64e5968
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'execute' function for the single-step flow. This

+function is called from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/ies/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/modelsim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/questa/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/riviera/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/vcs/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/README.txt
new file mode 100644
index 0000000..64e5968
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'execute' function for the single-step flow. This

+function is called from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt
new file mode 100644
index 0000000..8f2088a
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt
@@ -0,0 +1,32 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/3f90/hdl/util_vector_logic_v2_0_vl_rfs.v,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_7,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+xlslice_v1_0_vl_rfs.v,verilog,xlslice_v1_0_2,../../../../pb_logique_seq.gen/sources_1/bd/design_1/ipshared/11d0/hdl/xlslice_v1_0_vl_rfs.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xcelium/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt
new file mode 100644
index 0000000..9d37c1d
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################

+# Vivado (TM) v2020.2 (64-bit)

+#

+# README.txt: Please read the sections below to understand the steps required to

+#             run the exported script and information about the source files.

+#

+# Generated by export_simulation on Tue Jan 16 11:48:38 -0500 2024

+#

+################################################################################

+

+1. How to run the generated simulation script:-

+

+From the shell prompt in the current directory, issue the following command:-

+

+./design_1.sh

+

+This command will launch the 'compile', 'elaborate' and 'simulate' functions

+implemented in the script file for the 3-step flow. These functions are called

+from the main 'run' function in the script file.

+

+The 'run' function first executes the 'setup' function, the purpose of which is to

+create simulator specific setup files, create design library mappings and library

+directories and copy 'glbl.v' from the Vivado software install location into the

+current directory.

+

+The 'setup' function is also used for removing the simulator generated data in

+order to reset the current directory to the original state when export_simulation

+was launched from Vivado. This generated data can be removed by specifying the

+'-reset_run' switch to the './design_1.sh' script.

+

+./design_1.sh -reset_run

+

+To keep the generated data from the previous run but regenerate the setup files and

+library directories, use the '-noclean_files' switch.

+

+./design_1.sh -noclean_files

+

+For more information on the script, please type './design_1.sh -help'.

+

+2. Additional design information files:-

+

+export_simulation generates following additional file that can be used for fetching

+the design files information or for integrating with external custom scripts.

+

+Name   : file_info.txt

+Purpose: This file contains detail design file information based on the compile order

+         when export_simulation was executed from Vivado. The file contains information

+         about the file type, name, whether it is part of the IP, associated library

+         and the file path information.

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl
new file mode 100644
index 0000000..05f1b4f
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]

+if { [string length $curr_wave] == 0 } {

+  if { [llength [get_objects]] > 0} {

+    add_wave /

+    set_property needs_save false [current_wave_config]

+  } else {

+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

+  }

+}

+

+run -all

+quit

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h
new file mode 100644
index 0000000..f1321c6
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_0.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_0_H_
+#define _design_1_xlconstant_0_0_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_0 : public sc_module {
+  public:
+xlconstant_v1_1_7<8,0> mod;
+  sc_out< sc_bv<8> > dout;
+design_1_xlconstant_0_0 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h
new file mode 100644
index 0000000..c1a0432
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_1.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_1_H_
+#define _design_1_xlconstant_0_1_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_1 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_1 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h
new file mode 100644
index 0000000..f81da77
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_2.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_2_H_
+#define _design_1_xlconstant_0_2_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_2 : public sc_module {
+  public:
+xlconstant_v1_1_7<1,1> mod;
+  sc_out< sc_bv<1> > dout;
+design_1_xlconstant_0_2 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h
new file mode 100644
index 0000000..58f2af3
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/design_1_xlconstant_0_3.h
@@ -0,0 +1,65 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _design_1_xlconstant_0_3_H_
+#define _design_1_xlconstant_0_3_H_
+
+#include "xlconstant_v1_1_7.h"
+#include "systemc.h"
+class design_1_xlconstant_0_3 : public sc_module {
+  public:
+xlconstant_v1_1_7<24,1> mod;
+  sc_out< sc_bv<24> > dout;
+design_1_xlconstant_0_3 (sc_core::sc_module_name name);
+  };
+
+#endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt
new file mode 100644
index 0000000..b8b4e38
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/file_info.txt
@@ -0,0 +1,28 @@
+design_1_compteur_nbits_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd,

+design_1_mef_decod_i2s_v1b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd,

+design_1_reg_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd,

+design_1_reg_24b_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd,

+design_1_reg_dec_24b_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd,

+design_1_compteur_nbits_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd,

+design_1_mef_cod_i2s_vsb_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd,

+design_1_mux2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd,

+design_1_reg_dec_24b_fd_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd,

+design_1_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v,

+design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,

+design_1_xlconstant_0_1.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v,

+design_1_xlslice_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v,

+design_1_affhexPmodSSD_v3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd,

+design_1_calcul_param_1_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd,

+design_1_calcul_param_2_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd,

+design_1_calcul_param_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd,

+design_1_module_commande_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd,

+design_1_mux4_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd,

+design_1_mux4_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd,

+design_1_sig_fct_3_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd,

+design_1_sig_fct_sat_dure_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd,

+design_1_sig_fct_sat_dure_0_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd,

+design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,

+design_1_xlconstant_0_2.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v,

+design_1_xlconstant_0_3.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v,

+design_1.vhd,vhdl,xil_defaultlib,../../../bd/design_1/sim/design_1.vhd,

+glbl.v,Verilog,xil_defaultlib,glbl.v

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj
new file mode 100644
index 0000000..f281bb1
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj
@@ -0,0 +1,23 @@
+vhdl xil_defaultlib  \

+"../../../bd/design_1/ip/design_1_compteur_nbits_0_0/sim/design_1_compteur_nbits_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/sim/design_1_mef_decod_i2s_v1b_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_reg_24b_0_0/sim/design_1_reg_24b_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_reg_24b_0_1/sim/design_1_reg_24b_0_1.vhd" \

+"../../../bd/design_1/ip/design_1_reg_dec_24b_0_0/sim/design_1_reg_dec_24b_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_compteur_nbits_0_1/sim/design_1_compteur_nbits_0_1.vhd" \

+"../../../bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/sim/design_1_mef_cod_i2s_vsb_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_mux2_0_0/sim/design_1_mux2_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/sim/design_1_reg_dec_24b_fd_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/sim/design_1_affhexPmodSSD_v3_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_calcul_param_1_0_0/sim/design_1_calcul_param_1_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_calcul_param_2_0_0/sim/design_1_calcul_param_2_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_calcul_param_3_0_0/sim/design_1_calcul_param_3_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_module_commande_0_0/sim/design_1_module_commande_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_mux4_0_0/sim/design_1_mux4_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_mux4_0_1/sim/design_1_mux4_0_1.vhd" \

+"../../../bd/design_1/ip/design_1_sig_fct_3_0_0/sim/design_1_sig_fct_3_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/sim/design_1_sig_fct_sat_dure_0_0.vhd" \

+"../../../bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/sim/design_1_sig_fct_sat_dure_0_1.vhd" \

+"../../../bd/design_1/sim/design_1.vhd" \

+

+nosort

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj
new file mode 100644
index 0000000..4ba9ab7
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/vlog.prj
@@ -0,0 +1,12 @@
+verilog xil_defaultlib  \

+"../../../bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v" \

+"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \

+"../../../bd/design_1/ip/design_1_xlconstant_0_1/sim/design_1_xlconstant_0_1.v" \

+"../../../bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.v" \

+"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \

+"../../../bd/design_1/ip/design_1_xlconstant_0_2/sim/design_1_xlconstant_0_2.v" \

+"../../../bd/design_1/ip/design_1_xlconstant_0_3/sim/design_1_xlconstant_0_3.v" \

+

+verilog xil_defaultlib "glbl.v"

+

+nosort

diff --git a/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h
new file mode 100644
index 0000000..434d287
--- /dev/null
+++ b/pb_logique_seq.ip_user_files/sim_scripts/design_1/xsim/xlconstant_v1_1_7.h
@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:xlconstant:1.1
+// IP Revision: 1
+
+#ifndef _xlconstant_v1_1_7_H_
+#define _xlconstant_v1_1_7_H_
+
+#include "systemc.h"
+template<int CONST_WIDTH,int CONST_VAL>
+SC_MODULE(xlconstant_v1_1_7) {
+  public:
+  sc_out< sc_bv<CONST_WIDTH> > dout;
+  void init() {
+    dout.write(CONST_VAL);
+  }
+  SC_CTOR(xlconstant_v1_1_7) {
+    SC_METHOD(init);  
+  }
+};
+
+#endif
diff --git a/pb_logique_seq.sim/sim_1/behav/xsim/xelab.pb b/pb_logique_seq.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000..5e73e10
--- /dev/null
+++ b/pb_logique_seq.sim/sim_1/behav/xsim/xelab.pb
diff --git a/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc b/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc
new file mode 100644
index 0000000..78f6d59
--- /dev/null
+++ b/pb_logique_seq.srcs/constrs_1/imports/new/circuit_tr_signal.xdc
@@ -0,0 +1,318 @@
+## circuit_tr_signal.xdc 

+## This file is a general .xdc for the Zybo Z7 Rev. B

+## It is compatible with the Zybo Z7-20 and Zybo Z7-10

+## To use it in a project:

+## - uncomment the lines corresponding to used pins

+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

+

+## Adaptation projet demo_codec_zybo

+## D. Dalle, octobre 2018, janvier 2019

+##  ref Using Constraints 78

+#   UG903 (v2018.2) June 6, 2018

+##

+

+##Clock signal

+set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk

+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];

+

+

+##Switches (master)

+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]

+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]

+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]

+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]

+

+##Switches (demo_voltm_zybo, demo_codec_zybo)

+set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]

+set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]

+set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]

+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]

+

+###Switches (ThermoBin)

+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]

+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]

+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]

+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]

+

+##Buttons (master)

+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]

+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]

+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]

+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

+

+##Buttons (demo_voltm_zybo)

+set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]

+set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]

+set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]

+set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

+

+###Buttons (ThermoBin)

+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]

+#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]

+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]

+#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

+

+

+##LEDs   (master)

+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]

+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]

+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]

+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

+

+##LEDs   (demo_voltm_zybo, demo_codec_zybo_v1)

+set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L23P_T3_35 Sch=led[0]

+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L23N_T3_35 Sch=led[1]

+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_0_35 Sch=led[2]

+set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

+

+###LEDs   (ThermoBin)

+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L23P_T3_35 Sch=led[0]

+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L23N_T3_35 Sch=led[1]

+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_0_35 Sch=led[2]

+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

+

+##RGB LED 5 (Zybo Z7-20 only)

+#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r

+#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g

+#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b

+

+##RGB LED 6   (master)

+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r

+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g

+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

+

+##RGB LED 6   (demo_codec_zybo_v4)

+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { o_temoin1Hz }]; #IO_L18P_T2_34 Sch=led6_r

+set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { o_led6_r }]; #IO_L18P_T2_34 Sch=led6_r

+set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { o_led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g

+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g

+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

+

+

+##Audio Codec (master)

+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk

+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk

+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten

+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat

+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc

+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat

+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc

+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl

+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda

+ 

+##Audio Codec (demo_codec_zybo_v1)

+set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { o_ac_bclk }];   #IO_0_34 Sch=ac_bclk

+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { o_ac_mclk }];   #IO_L19N_T3_VREF_34 Sch=ac_mclk

+set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { o_ac_muten }];  #IO_L23N_T3_34 Sch=ac_muten

+set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { o_ac_pbdat }];  #IO_L20N_T3_34 Sch=ac_pbdat

+set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { o_ac_pblrc }];  #IO_25_34 Sch=ac_pblrc

+set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { i_ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat

+set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { o_ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc

+set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { io_ac_scl }];    #IO_L13P_T2_MRCC_34 Sch=ac_scl

+set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { io_ac_sda }];   #IO_L23P_T3_34 Sch=ac_sda 

+##Audio Codec/external EEPROM IIC bus

+##set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports iic_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL

+##set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports iic_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA

+

+ 

+######## zybo-z7-dma.xdc

+###I2S Audio Codec

+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK

+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK

+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN

+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT

+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC

+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT

+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC

+###Audio Codec/external EEPROM IIC bus

+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports iic_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL

+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports iic_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA

+

+ 

+##Additional Ethernet signals

+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b

+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b

+

+

+##USB-OTG over-current detect pin

+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc

+

+

+##Fan (Zybo Z7-20 only)

+#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu

+

+

+##HDMI RX

+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd

+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl

+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda

+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n

+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p

+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]

+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]

+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]

+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]

+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]

+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33     } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]

+

+##HDMI RX CEC (Zybo Z7-20 only)

+#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec

+

+

+##HDMI TX

+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd

+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl

+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda

+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n

+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p

+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]

+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]

+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]

+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]

+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]

+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33     } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]

+

+##HDMI TX CEC 

+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec

+ 

+##Pmod Header JA (XADC), (MASTER),

+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p		   

+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P             

+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P            

+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P             

+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N        

+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N             

+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N            

+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N             

+ 

+#demo_sync_zybo demo_codec_zybo

+###Pmod Header JA (demo_sync_zybo, demo_codec_zybo branchement: PmodSSD),                                                                                                  #  pmod8LD 

+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p		#  pmod haut   

+set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P          #  pmod haut   

+set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P         #  pmod haut    

+set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P          #  pmod haut   

+set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N    #  pmod bas  

+set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N         #  pmod bas  

+set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N        #  pmod bas

+set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { o_pmodssd[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N         #  pmod bas

+

+

+###Pmod Header JB (Zybo Z7-20 only)

+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33     } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]		 

+#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVCMOS33     } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]         

+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33     } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]        

+#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33     } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]        

+#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33     } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]        

+#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33     } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]        

+#set_property -dict { PACKAGE_PIN V6    IOSTANDARD LVCMOS33     } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]             

+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33     } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]             

+                                                                                                                                                                                                                                                              

+###Pmod Header JC (master)                                                                                                               

+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1] 		 

+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]   

+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]

+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]       

+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]              

+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]

+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]      

+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33     } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]       

+

+

+##Pmod Header JC (demo_sync_zybo: compteur , demo_codec_zybo :    )                                                                                                               

+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]     #  pmod haut		 

+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]     #  pmod haut	     

+set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]      #  pmod haut

+set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]      #  pmod haut   

+set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]      # pmod bas        

+set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]      # pmod bas       

+set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]      # pmod bas        

+set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33     } [get_ports { o_pmodled[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]      # pmod bas

+ 

+

+

+##Pmod Header JD   (master)                                                                                                                

+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]                  

+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]				 

+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]                  

+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]             

+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]            

+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]            

+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]             

+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]             

+           

+# #Pmod Header JD   (demo_codec_zybo: signaux de tests version 3b  )                                                                                                           

+# set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { DIO[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]            # # pmod haut       

+# set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { DIO[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]            # # pmod haut       

+# set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { DIO[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]            # # pmod haut      

+# set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { DIO[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]       # # pmod haut       

+# set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { DIO[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]   ## pmod bas          

+# set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { DIO[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]   ## pmod bas         

+# set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { DIO[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]    ## pmod bas         

+# set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { DIO[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]    ## pmod bas         

+ 

+                                                                                                                        

+                                                                                                                                                                                                                                                              

+# # Pmod Header JE   ((demo_codec_zybo_v3b: signaux de tests revision 9 janvier 2019 )   rev v3 )                                                                                                                

+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { DIO[8] }]; #IO_L4P_T0_34 Sch=je[1]                         

+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { DIO[9] }]; #IO_L18N_T2_34 Sch=je[2]                     

+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { DIO[10] }]; #IO_25_35 Sch=je[3]                          

+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DIO[11] }]; #IO_L19P_T3_35 Sch=je[4]                     

+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { DIO[12] }]; #IO_L3N_T0_DQS_34 Sch=je[7]                  

+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { DIO[13] }]; #IO_L9N_T1_DQS_34 Sch=je[8]                  

+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { DIO[14] }]; #IO_L20P_T3_34 Sch=je[9]                     

+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { DIO[15] }]; #IO_L7N_T1_34 Sch=je[10]          

+

+                                                                                                                                                                                                                                                              

+##Pmod Header JE   (master)                                                                                                                

+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]						 

+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]                     

+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]                          

+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]                     

+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]                  

+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]                  

+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]                     

+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]                    

+

+

+

+##Pcam MIPI CSI-2 Connector

+## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk

+#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]

+#set_property INTERNAL_VREF 0.6 [get_iobanks 35]

+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n

+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p

+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]

+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]

+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]

+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]

+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n

+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p

+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]

+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]

+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]

+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]

+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk

+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 	PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio

+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl

+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda

+ 

+ 

+##Unloaded Crypto Chip SWI (for future use)

+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda

+ 

+ 

+##Unconnected Pins (Zybo Z7-20 only)

+#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13

+#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13

+#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13

+#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13

+#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13

+#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13

+#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13

+#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13

+#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13

+#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13

+#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13

+#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13

+

+

diff --git a/pb_logique_seq.srcs/sim_1/imports/new/module_commande_tb.vhd b/pb_logique_seq.srcs/sim_1/imports/new/module_commande_tb.vhd
new file mode 100644
index 0000000..2b2db15
--- /dev/null
+++ b/pb_logique_seq.srcs/sim_1/imports/new/module_commande_tb.vhd
@@ -0,0 +1,177 @@
+---------------------------------------------------------------------------------------------
+-- Test-Bench module_commande_tb.vhd
+--  
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Date            : 6 mai 2020
+-- Auteur(s)       : Audrey Corbeil-Therrien, Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2019.1
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Developpement d'un test bench pour la problématique de logique séquentielle
+-- Test unitaire de module_commande
+---------------------------------------------------------------------------------------------
+-- Révisions
+-- bouton suivant & précédent 29 avril
+-- À faire :
+--
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity module_commande_tb is
+--  Port ( );
+end module_commande_tb;
+
+architecture Behavioral of module_commande_tb is
+
+
+component module_commande
+generic (nbtn : integer := 4;  mode_simulation: std_logic := '1');
+    PORT (
+          clk          : in  std_logic;
+          o_reset      : out  std_logic; 
+          i_btn        : in  std_logic_vector (nbtn-1 downto 0); -- signaux directs des boutons
+          i_sw         : in  std_logic_vector (3 downto 0);      -- signaux directs des interrupteurs
+          o_btn_cd     : out std_logic_vector (nbtn-1 downto 0); -- signaux conditionnés 
+                                                                 -- (debounced) des boutons
+          --o_btn_strb : out std_logic_vector (nbtn-1 downto 0); -- impulsion 
+          o_selection_par  :  out std_logic_vector(1 downto 0);
+          o_selection_fct  :  out std_logic_vector(1 downto 0)
+          );
+end component;
+
+
+-- l'horloge devrait être 50 MHz
+   signal   d_clk_p       :  std_logic := '0';   -- (sol) horloge principale 50 MHz (utile pour cette simulation a éviter si possible)
+   signal   d_reset       :  std_logic := '0'; 
+   signal   d_sw          :  std_logic_vector (3 downto 0);  -- 4 bits sur Zybo
+   signal   d_btn         :  std_logic_vector (3 downto 0);
+   
+   signal   d_btn_db      :  std_logic_vector (3 downto 0);
+   signal   d_sel_par     :  std_logic_vector (1 downto 0); 
+   signal   d_sel_fct     :  std_logic_vector (1 downto 0);
+   
+   -- signal test pour vérification
+   signal expected_status_code    : std_logic_vector (1 downto 0);
+
+   constant c_clk_p_Period      : time :=  20 ns;  -- 50 MHz  -- frequence de l'horloge utilisee pour module_commande dans la problématique
+   constant c_delai_commandes   : time :=  10 us;  -- delai entre commandes du bouton
+   
+   
+begin
+
+   ----------------------------------------------------------------------------
+   -- unites objets du test  
+   ----------------------------------------------------------------------------
+     
+ UUT: module_commande
+ Port map
+    ( 
+      clk             =>  d_clk_p,
+      o_reset         =>  open,
+      i_btn           =>  d_btn,
+      i_sw            =>  d_sw,
+      o_btn_cd        =>  d_btn_db,
+      o_selection_par =>  d_sel_par,
+      o_selection_fct =>  d_sel_fct
+  );
+
+   ----------------------------------------------------------------------------
+   -- generation horloge  
+   ----------------------------------------------------------------------------
+   
+  sim_clk_p:  process
+   begin
+      d_clk_p <= '1';  -- init
+      loop
+         wait for c_clk_p_Period / 2;
+         d_clk_p <= not d_clk_p; -- invert clock value
+      end loop;
+   end process;  
+   
+----------------------------------------------------------------------------
+-- reset par btn(3)
+----------------------------------------------------------------------------
+d_reset <= d_btn(3);
+
+
+
+tb : PROCESS
+   BEGIN
+      d_sw  <= "0000";
+      wait for 100 ns;  
+      d_btn <= "1000", "0000" after 10 * c_clk_p_Period;  -- application reset sur btn3
+      
+     -- Tests avec les interrupteurs
+     for i_sw in 0 to 15 loop
+          d_sw <= std_logic_vector(to_unsigned(i_sw,4));
+           wait for c_delai_commandes;  -- attendre delai
+      end loop;
+      d_sw  <= "0000";
+      
+      -- tests du plan de vérification de la MEF pour boutons
+      expected_status_code <= "00";
+      d_btn <= "1000", "0000" after 10 * c_clk_p_Period;  -- application reset sur btn3
+          wait for 10.1 * c_clk_p_Period;  -- attendre delai
+          assert (d_sel_fct = expected_status_code)
+            report "L'etat n'est pas S0 après la reinitialisation"
+            severity WARNING;
+      for index_btn in 0 to 7 loop
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0001";
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0000";
+          -- incrementation du code de l'état attendu
+          expected_status_code <= std_logic_vector( unsigned(expected_status_code) + 1 );
+          assert (d_sel_fct = expected_status_code)
+            report "L'etat n'est pas celui attendu"
+            severity WARNING;
+      end loop;
+      for index_btn in 0 to 7 loop
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0010";
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0000"; 
+          expected_status_code <= std_logic_vector( unsigned(expected_status_code) - 1 );
+          assert (d_sel_fct = expected_status_code)
+            report "L'etat n'est pas celui attendu"
+            severity WARNING;
+      end loop;
+      for index_btn in 0 to 3 loop
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0011";
+          wait for c_delai_commandes;  -- attendre delai
+          d_btn <= "0000"; 
+          -- Pas de assert ici - on explore le comportement d'une condition particuliere
+      end loop;
+
+
+      d_sw  <= "0000";
+      d_btn <= "0000";
+      
+      WAIT; -- will wait forever
+   END PROCESS;
+
+
+end Behavioral;
+
+
+
+
diff --git a/pb_logique_seq.srcs/sim_1/imports/new/simul_module_sig_tb.vhd b/pb_logique_seq.srcs/sim_1/imports/new/simul_module_sig_tb.vhd
new file mode 100644
index 0000000..b94fe01
--- /dev/null
+++ b/pb_logique_seq.srcs/sim_1/imports/new/simul_module_sig_tb.vhd
@@ -0,0 +1,294 @@
+---------------------------------------------------------------------------------------------
+-- Test-Bench simul_module_sig_tb.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 10 janvier 2020
+-- Auteur(s)       :
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2019.1
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Developpement d'un test bench pour la problématique de logique séquentielle
+-- Test unitaire de module_sig
+---------------------------------------------------------------------------------------------
+-- À FAIRE POUR L'APP - ADAPTER POUR PLAN DE VÉRIFICATION
+--  voir ligne 358
+---------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use STD.textio.all;
+use ieee.std_logic_textio.all;
+
+entity simul_module_sig_tb is
+--  Port ( );
+end simul_module_sig_tb;
+
+architecture Behavioral of simul_module_sig_tb is
+
+file leftInputFile : text;
+file rightInputFile : text;
+--Chemin depuis le fichier de simulation les fichiers se trouvent à la racine du projet
+constant leftInputFileName : string := "../../../../leftInput.txt"; 
+constant rightInputFileName : string := "../../../../rightInput.txt";
+
+shared variable fstatusLeft : file_open_status := NAME_ERROR;
+shared variable fstatusRight : file_open_status := NAME_ERROR;
+
+-- le codeur I2S est utlisé pour générer le flot I2S
+component M9_codeur_i2s_imp_1VJCTGL
+  Port (
+      i_bclk      : in std_logic;
+      i_reset      : in std_logic;
+      i_lrc       : in std_logic;
+      i_dat_left  : in  std_logic_vector(23 downto 0);
+      i_dat_right : in  std_logic_vector(23 downto 0);
+      o_dat       : out std_logic_vector(0 downto 0)
+  );
+end component;
+
+component M1_decodeur_i2s_imp_17RYJKZ
+  Port (
+      clk      : in std_logic;
+      i_reset      : in std_logic;
+      i_lrc       : in std_logic;
+      i_data       : in std_logic;
+      o_dat_left  : out  std_logic_vector(23 downto 0);
+      o_dat_right : out  std_logic_vector(23 downto 0);
+      o_str_dat   : out std_logic
+);
+end component;
+
+
+  component design_1 is
+  port (
+    i_recdat : in STD_LOGIC;
+    i_lrc : in STD_LOGIC;
+    i_btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    clk_100MHz : in STD_LOGIC;
+    o_pbdat : out STD_LOGIC_VECTOR ( 0 to 0 );
+    JPmod : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_param : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_sel_fct : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1;
+  
+impure function nextLeftInput return std_logic_vector is 
+variable iline : line;
+variable data: std_logic_vector(23 downto 0);
+begin  
+    if(fstatusLeft /= OPEN_OK or endfile(leftInputFile)) then 
+        file_open(fstatusLeft, leftInputFile, leftInputFileName);
+    end if;
+    if(fstatusLeft = OPEN_OK and not endfile(leftInputFile)) then
+        readline(leftInputFile, iline);
+        hread(iline, data);
+        return data;
+    else
+        return x"000000";
+    end if;
+end nextLeftInput;
+ 
+impure function nextRightInput return std_logic_vector is 
+variable iline : line;
+variable data: std_logic_vector(23 downto 0);
+begin  
+    if(fstatusRight /= OPEN_OK or endfile(rightInputFile)) then 
+        file_open(fstatusRight, rightInputFile, rightInputFileName);
+    end if;
+    if(fstatusRight = OPEN_OK and not endfile(rightInputFile)) then
+        readline(rightInputFile, iline);
+        hread(iline, data);
+        return data;
+    else
+        return x"000000";
+    end if;
+end nextRightInput;
+ 
+    signal   d_ac_bclk     : std_logic := '0';   -- bit clock ... horloge I2S digital audio
+    signal   d_ac_mclk     : std_logic := '0';   -- Master Clock horloge 12.288 MHz
+    signal   d_cpt_mclk    : std_logic_vector (7 downto 0) := "00000000";
+    
+    signal   d_ac_pbdat    : std_logic := '0';   -- I²S (Playback Data)
+    signal   d_sig_pbdat   : std_logic;   -- I²S (Playback Data)
+  
+    signal   d_ac_pblrc    : std_logic := '0';  -- I²S (Playback Channel Clock) DAC Sampling Rate Clock,
+    signal   d_ac_recdat   : std_logic;  -- I²S (Record Data)
+    signal   d_ac_reclrc   : std_logic := '0';  -- I²S (Record Channel Clock)   ADC Sampling Rate Clock,
+    
+ -- source I2S simulee
+    signal  d_val_ech_L    : std_logic_vector(23 downto 0) := (others =>'0') ;  -- ech source simulee canal gauche
+    signal  d_val_ech_R    : std_logic_vector(23 downto 0) := (others =>'0') ;  -- ech source simulee canal droite
+    signal  d_val_ech_R_u  : std_logic_vector(23 downto 0) := (others =>'0');   -- ech source simulee transforme pour affichage
+    signal  d_val_ech_L_u  : std_logic_vector(23 downto 0) := (others =>'0');   -- ech source simulee transforme pour affichage
+    signal  d_ech_reg_left : std_logic_vector(23 downto 0) := (others =>'0');    -- echantillon canal gauche
+    signal  d_ech_reg_right: std_logic_vector(23 downto 0) := (others =>'0');    -- echantillon canal droite
+
+    --signal s_ech_gen : std_logic_vector(23 downto 0) := (others =>'0');
+    signal s_reset   : std_logic;
+    signal compt_gen_R, compt_gen_L  : unsigned(7 downto 0) := x"00";
+    
+    signal s_btn    : std_logic_vector(3 downto 0):= (others =>'0');
+    signal s_sw    : std_logic_vector(3 downto 0):= (others =>'0');
+    signal d_param      : std_logic_vector(7 downto 0):= (others =>'0');
+    signal d_led        : std_logic_vector(3 downto 0):= (others =>'0');
+    
+-- notes
+    -- frequences      ***********************
+    -- d_ac_reclrc  ~ 48.    KHz    (~ 20.8    us)
+    -- d_ac_mclk,   ~ 12.288 MHz    (~ 80,715  ns)
+    -- d_ac_bclk    ~ 3,10   MHz    (~ 322,857 ns) freq mclk/4
+    -- La durée d'une période reclrc est de 64,5 périodes de bclk ... ARRONDI a 64 pour simul
+    --   
+    constant c_mclk_Period       : time :=  80.715 ns;  -- 12.288 MHz
+    constant c_clk_p_Period      : time :=   8     ns;  -- 125 MHz
+    
+
+
+begin
+   ----------------------------------------------------------------------------
+   -- unites objets du test
+   ----------------------------------------------------------------------------
+     
+ UUT_codeur: M9_codeur_i2s_imp_1VJCTGL
+ Port map
+    (
+      i_bclk      =>  d_ac_bclk,
+      i_reset     =>  s_reset,
+      i_lrc       =>  d_ac_pblrc,
+      i_dat_left  =>  d_val_ech_L,
+      i_dat_right =>  d_val_ech_R,
+      o_dat(0)    =>  d_ac_recdat
+  );
+
+  
+  UUT_mod_sig: design_1
+   Port map
+      (
+        clk_100MHz  =>  d_ac_bclk,
+        i_lrc       =>  d_ac_pblrc,
+        i_recdat      =>  d_ac_recdat,
+        i_sw        =>  s_sw,
+        i_btn       => s_btn,
+        o_pbdat(0)       =>  d_sig_pbdat,
+        o_param     =>  d_param,
+        o_sel_fct    =>  d_led(3 downto 2),
+        o_sel_par    =>  d_led(1 downto 0)
+    );
+  
+    --prevu pour test d'un decodeur
+    UUT_decodeur: M1_decodeur_i2s_imp_17RYJKZ
+     Port map
+        (
+          clk      =>  d_ac_bclk,
+          i_reset     =>  s_reset,
+          i_lrc       =>  d_ac_pblrc,
+          i_data       =>  d_sig_pbdat,
+          o_dat_left  =>  d_ech_reg_left,
+          o_dat_right =>  d_ech_reg_right,
+          o_str_dat   =>  open
+      );
+    
+  
+  
+   ----------------------------------------------------------------------------
+   -- generation horloge
+   ----------------------------------------------------------------------------
+   
+  sim_mclk:  process
+      begin
+         d_ac_mclk <= '1';  -- init
+         loop
+            wait for c_mclk_Period / 2;
+            d_ac_mclk <= not d_ac_mclk;
+         end loop;
+      end process;
+   
+   
+  sim_cpt_bclk: process (d_ac_mclk)
+     begin
+         if rising_edge(d_ac_mclk) then
+               d_cpt_mclk<= d_cpt_mclk + 1;
+         end if;
+     end process sim_cpt_bclk;
+
+----------------------------------------------------------------------------
+-- generation signal s_ech_gen par lecture de la table de valeurs
+----------------------------------------------------------------------------
+sim_entree_D : process (s_reset, d_ac_pblrc)
+begin
+   if(s_reset = '1') then  -- Init/reset
+      compt_gen_R <= x"00";
+      d_val_ech_R <= X"000000";
+   else
+      if(d_ac_pblrc'event and d_ac_pblrc = '1') then
+          d_val_ech_R <= nextRightInput;
+      end if;
+   end if;
+end process;
+
+sim_entree_G : process (s_reset, d_ac_pblrc)
+begin
+   if(s_reset = '1') then  -- Init/reset
+      compt_gen_L <= x"00";
+      d_val_ech_L <= X"000000";
+   else
+      if(d_ac_pblrc'event and d_ac_pblrc = '0') then
+         d_val_ech_L <= nextLeftInput;
+      end if;
+   end if;
+end process;
+
+ d_ac_bclk   <= d_cpt_mclk(1);
+ d_ac_pblrc <=  d_ac_reclrc;                 -- identique a reclrc
+ d_val_ech_R_u <=  d_val_ech_R + x"800000";  -- pour afficher dans un format analogique
+ d_val_ech_L_u <=  d_val_ech_L + x"800000";  -- pour afficher dans un format analogique
+ 
+-- synchro sur front descendant bclk
+ lrc_proc: process(d_ac_bclk)
+   begin
+     if falling_edge(d_ac_bclk) then
+            d_ac_reclrc <= d_cpt_mclk(7);
+         end if;
+     end process lrc_proc;
+
+  -- Le processus suivant cree une copie au front mclk (4 fois plus rapide que bclk)
+  -- ou le d_ac_recdat genere par le codeur I2S simulé est redirigé vers d_ac_pbdat
+  -- (peut être utile pour un test unitaire de décodeur)
+  -- Noter que le module module_sig est connecté à d_sig_pbdat
+  --
+  inst_sortie_pb_dat : process(d_ac_mclk)
+     begin
+         if rising_edge(d_ac_mclk) then
+             d_ac_pbdat  <=  d_ac_recdat;         --
+         end if;
+     end process;
+     
+----------------------------------------------------------------------------------------------------------------------
+  --  BANC DE TEST GLOBAL --
+  --  Nous vous présentons une simulation de base générique
+  --  Vous devez changer les lignes ci-dessous pour concorder avec votre plan de vérification
+----------------------------------------------------------------------------------------------------------------------
+  tb : PROCESS
+     BEGIN
+        --
+       
+        s_reset <= '1';
+        s_btn <= "1000";
+        wait for 2 us;
+        s_reset <= '0';
+        s_btn <= "0000";
+        s_sw <= "0000";
+        wait for 40 us;
+                 
+        WAIT; -- will wait forever
+     END PROCESS;
+
+end Behavioral;
\ No newline at end of file
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/design_1.bd b/pb_logique_seq.srcs/sources_1/bd/design_1/design_1.bd
new file mode 100644
index 0000000..2f07b8c
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/design_1.bd
@@ -0,0 +1,1505 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0xD5C48FBFC0647294",
+      "device": "xc7z010clg400-1",
+      "gen_directory": "../../../../pb_logique_seq.gen/sources_1/bd/design_1",
+      "name": "design_1",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2020.2"
+    },
+    "design_tree": {
+      "M1_decodeur_i2s": {
+        "compteur_7bits": "",
+        "MEF_decodeur_i2s": "",
+        "registre_24bits_droite": "",
+        "registre_24bits_gauche": "",
+        "registre_decalage_24bits": "",
+        "xlconstant_0": "",
+        "xlconstant_1": ""
+      },
+      "M9_codeur_i2s": {
+        "compteur_nbits_0": "",
+        "mef_cod_i2s_vsb_0": "",
+        "mux2_0": "",
+        "reg_dec_24b_fd_0": "",
+        "util_vector_logic_0": "",
+        "xlconcat_0": "",
+        "xlconstant_0": "",
+        "xlslice_0": ""
+      },
+      "M10_conversion_affichage": "",
+      "M5_parametre_1": "",
+      "M6_parametre_2": "",
+      "M7_parametre_3": "",
+      "Multiplexeur_choix_fonction": "",
+      "Multiplexeur_choix_parametre": "",
+      "M4_fonction3": "",
+      "M2_fonction_distortion_dure1": "",
+      "M3_fonction_distorsion_dure2": "",
+      "parametre_0": "",
+      "M8_commande": ""
+    },
+    "ports": {
+      "i_recdat": {
+        "direction": "I"
+      },
+      "i_lrc": {
+        "direction": "I"
+      },
+      "i_btn": {
+        "direction": "I",
+        "left": "3",
+        "right": "0"
+      },
+      "i_sw": {
+        "direction": "I",
+        "left": "3",
+        "right": "0"
+      },
+      "clk_100MHz": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "FREQ_HZ": {
+            "value": "100000000"
+          }
+        }
+      },
+      "o_pbdat": {
+        "direction": "O",
+        "left": "0",
+        "right": "0"
+      },
+      "JPmod": {
+        "direction": "O",
+        "left": "7",
+        "right": "0"
+      },
+      "o_param": {
+        "direction": "O",
+        "left": "7",
+        "right": "0"
+      },
+      "o_sel_par": {
+        "direction": "O",
+        "left": "1",
+        "right": "0"
+      },
+      "o_sel_fct": {
+        "direction": "O",
+        "left": "1",
+        "right": "0"
+      }
+    },
+    "components": {
+      "M1_decodeur_i2s": {
+        "ports": {
+          "o_str_dat": {
+            "direction": "O"
+          },
+          "o_dat_left": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          },
+          "o_dat_right": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          },
+          "clk": {
+            "direction": "I"
+          },
+          "i_data": {
+            "direction": "I"
+          },
+          "i_lrc": {
+            "direction": "I"
+          },
+          "i_reset": {
+            "direction": "I"
+          }
+        },
+        "components": {
+          "compteur_7bits": {
+            "vlnv": "xilinx.com:module_ref:compteur_nbits:1.0",
+            "xci_name": "design_1_compteur_7bits_0",
+            "xci_path": "ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/compteur_7bits",
+            "parameters": {
+              "nbits": {
+                "value": "7"
+              }
+            },
+            "reference_info": {
+              "ref_type": "hdl",
+              "ref_name": "compteur_nbits",
+              "boundary_crc": "0x0"
+            },
+            "ports": {
+              "clk": {
+                "type": "clk",
+                "direction": "I",
+                "parameters": {
+                  "ASSOCIATED_RESET": {
+                    "value": "reset",
+                    "value_src": "constant"
+                  },
+                  "FREQ_HZ": {
+                    "value": "100000000",
+                    "value_src": "user_prop"
+                  },
+                  "CLK_DOMAIN": {
+                    "value": "design_1_clk_100MHz",
+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_en": {
+                "direction": "I"
+              },
+              "reset": {
+                "type": "rst",
+                "direction": "I"
+              },
+              "o_val_cpt": {
+                "direction": "O",
+                "left": "6",
+                "right": "0"
+              }
+            }
+          },
+          "MEF_decodeur_i2s": {
+            "vlnv": "xilinx.com:module_ref:mef_decod_i2s_v1b:1.0",
+            "xci_name": "design_1_MEF_decodeur_i2s_0",
+            "xci_path": "ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/MEF_decodeur_i2s",
+            "reference_info": {
+              "ref_type": "hdl",
+              "ref_name": "mef_decod_i2s_v1b",
+              "boundary_crc": "0x0"
+            },
+            "ports": {
+              "i_bclk": {
+                "direction": "I",
+                "parameters": {
+                  "FREQ_HZ": {
+                    "value": "100000000",
+                    "value_src": "user_prop"
+                  },
+                  "PHASE": {
+                    "value": "0.000",
+                    "value_src": "default_prop"
+                  },
+                  "CLK_DOMAIN": {
+                    "value": "design_1_clk_100MHz",
+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_reset": {
+                "type": "rst",
+                "direction": "I"
+              },
+              "i_lrc": {
+                "direction": "I"
+              },
+              "i_cpt_bits": {
+                "direction": "I",
+                "left": "6",
+                "right": "0"
+              },
+              "o_bit_enable": {
+                "direction": "O"
+              },
+              "o_load_left": {
+                "direction": "O"
+              },
+              "o_load_right": {
+                "direction": "O"
+              },
+              "o_str_dat": {
+                "direction": "O"
+              },
+              "o_cpt_bit_reset": {
+                "type": "rst",
+                "direction": "O"
+              }
+            }
+          },
+          "registre_24bits_droite": {
+            "vlnv": "xilinx.com:module_ref:reg_24b:1.0",
+            "xci_name": "design_1_registre_24bits_droite_0",
+            "xci_path": "ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/registre_24bits_droite",
+            "reference_info": {
+              "ref_type": "hdl",
+              "ref_name": "reg_24b",
+              "boundary_crc": "0x0"
+            },
+            "ports": {
+              "i_clk": {
+                "type": "clk",
+                "direction": "I",
+                "parameters": {
+                  "ASSOCIATED_RESET": {
+                    "value": "i_reset",
+                    "value_src": "constant"
+                  },
+                  "FREQ_HZ": {
+                    "value": "100000000",
+                    "value_src": "user_prop"
+                  },
+                  "CLK_DOMAIN": {
+                    "value": "design_1_clk_100MHz",
+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_reset": {
+                "type": "rst",
+                "direction": "I"
+              },
+              "i_en": {
+                "direction": "I"
+              },
+              "i_dat": {
+                "direction": "I",
+                "left": "23",
+                "right": "0"
+              },
+              "o_dat": {
+                "direction": "O",
+                "left": "23",
+                "right": "0"
+              }
+            }
+          },
+          "registre_24bits_gauche": {
+            "vlnv": "xilinx.com:module_ref:reg_24b:1.0",
+            "xci_name": "design_1_registre_24bits_gauche_0",
+            "xci_path": "ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/registre_24bits_gauche",
+            "reference_info": {
+              "ref_type": "hdl",
+              "ref_name": "reg_24b",
+              "boundary_crc": "0x0"
+            },
+            "ports": {
+              "i_clk": {
+                "type": "clk",
+                "direction": "I",
+                "parameters": {
+                  "ASSOCIATED_RESET": {
+                    "value": "i_reset",
+                    "value_src": "constant"
+                  },
+                  "FREQ_HZ": {
+                    "value": "100000000",
+                    "value_src": "user_prop"
+                  },
+                  "CLK_DOMAIN": {
+                    "value": "design_1_clk_100MHz",
+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_reset": {
+                "type": "rst",
+                "direction": "I"
+              },
+              "i_en": {
+                "direction": "I"
+              },
+              "i_dat": {
+                "direction": "I",
+                "left": "23",
+                "right": "0"
+              },
+              "o_dat": {
+                "direction": "O",
+                "left": "23",
+                "right": "0"
+              }
+            }
+          },
+          "registre_decalage_24bits": {
+            "vlnv": "xilinx.com:module_ref:reg_dec_24b:1.0",
+            "xci_name": "design_1_registre_decalage_24bits_0",
+            "xci_path": "ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/registre_decalage_24bits",
+            "reference_info": {
+              "ref_type": "hdl",
+              "ref_name": "reg_dec_24b",
+              "boundary_crc": "0x0"
+            },
+            "ports": {
+              "i_clk": {
+                "type": "clk",
+                "direction": "I",
+                "parameters": {
+                  "ASSOCIATED_RESET": {
+                    "value": "i_reset",
+                    "value_src": "constant"
+                  },
+                  "FREQ_HZ": {
+                    "value": "100000000",
+                    "value_src": "user_prop"
+                  },
+                  "CLK_DOMAIN": {
+                    "value": "design_1_clk_100MHz",
+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_reset": {
+                "type": "rst",
+                "direction": "I"
+              },
+              "i_load": {
+                "direction": "I"
+              },
+              "i_en": {
+                "direction": "I"
+              },
+              "i_dat_bit": {
+                "direction": "I"
+              },
+              "i_dat_load": {
+                "direction": "I",
+                "left": "23",
+                "right": "0"
+              },
+              "o_dat": {
+                "direction": "O",
+                "left": "23",
+                "right": "0"
+              }
+            }
+          },
+          "xlconstant_0": {
+            "vlnv": "xilinx.com:ip:xlconstant:1.1",
+            "xci_name": "design_1_xlconstant_0_0",
+            "xci_path": "ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/xlconstant_0"
+          },
+          "xlconstant_1": {
+            "vlnv": "xilinx.com:ip:xlconstant:1.1",
+            "xci_name": "design_1_xlconstant_1_0",
+            "xci_path": "ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci",
+            "inst_hier_path": "M1_decodeur_i2s/xlconstant_1",
+            "parameters": {
+              "CONST_WIDTH": {
+                "value": "24"
+              }
+            }
+          }
+        },
+        "nets": {
+          "reg_dec_24b_0_o_dat": {
+            "ports": [
+              "registre_decalage_24bits/o_dat",
+              "registre_24bits_droite/i_dat",
+              "registre_24bits_gauche/i_dat"
+            ]
+          },
+          "mef_decod_i2s_v1b_0_o_load_left": {
+            "ports": [
+              "MEF_decodeur_i2s/o_load_left",
+              "registre_24bits_gauche/i_en"
+            ]
+          },
+          "mef_decod_i2s_v1b_0_o_load_right": {
+            "ports": [
+              "MEF_decodeur_i2s/o_load_right",
+              "registre_24bits_droite/i_en"
+            ]
+          },
+          "mef_decod_i2s_v1b_0_o_str_dat": {
+            "ports": [
+              "MEF_decodeur_i2s/o_str_dat",
+              "o_str_dat"
+            ]
+          },
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+              "registre_24bits_gauche/o_dat",
+              "o_dat_left"
+            ]
+          },
+          "reg_24b_0_o_dat": {
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+              "registre_24bits_droite/o_dat",
+              "o_dat_right"
+            ]
+          },
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+            "ports": [
+              "clk",
+              "compteur_7bits/clk",
+              "MEF_decodeur_i2s/i_bclk",
+              "registre_24bits_droite/i_clk",
+              "registre_24bits_gauche/i_clk",
+              "registre_decalage_24bits/i_clk"
+            ]
+          },
+          "mef_decod_i2s_v1b_0_o_cpt_bit_reset": {
+            "ports": [
+              "MEF_decodeur_i2s/o_cpt_bit_reset",
+              "compteur_7bits/reset"
+            ]
+          },
+          "mef_decod_i2s_v1b_0_o_bit_enable": {
+            "ports": [
+              "MEF_decodeur_i2s/o_bit_enable",
+              "compteur_7bits/i_en",
+              "registre_decalage_24bits/i_en"
+            ]
+          },
+          "i_data_1": {
+            "ports": [
+              "i_data",
+              "registre_decalage_24bits/i_dat_bit"
+            ]
+          },
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+              "i_lrc",
+              "MEF_decodeur_i2s/i_lrc"
+            ]
+          },
+          "compteur_nbits_0_o_val_cpt": {
+            "ports": [
+              "compteur_7bits/o_val_cpt",
+              "MEF_decodeur_i2s/i_cpt_bits"
+            ]
+          },
+          "i_reset_1": {
+            "ports": [
+              "i_reset",
+              "MEF_decodeur_i2s/i_reset",
+              "registre_24bits_droite/i_reset",
+              "registre_24bits_gauche/i_reset",
+              "registre_decalage_24bits/i_reset"
+            ]
+          },
+          "xlconstant_0_dout": {
+            "ports": [
+              "xlconstant_0/dout",
+              "registre_decalage_24bits/i_load"
+            ]
+          },
+          "xlconstant_1_dout": {
+            "ports": [
+              "xlconstant_1/dout",
+              "registre_decalage_24bits/i_dat_load"
+            ]
+          }
+        }
+      },
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+            "left": "23",
+            "right": "0"
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+            "direction": "I"
+          },
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+          },
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+            "right": "0"
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+            "inst_hier_path": "M9_codeur_i2s/compteur_nbits_0",
+            "parameters": {
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+                "value": "7"
+              }
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+              "ref_name": "compteur_nbits",
+              "boundary_crc": "0x0"
+            },
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+                "direction": "I",
+                "parameters": {
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+                    "value_src": "constant"
+                  },
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+                    "value_src": "user_prop"
+                  },
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+                    "value_src": "default_prop"
+                  }
+                }
+              },
+              "i_en": {
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+              },
+              "reset": {
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+                "direction": "I"
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+                "right": "0"
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+                "parameters": {
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+                    "value_src": "user_prop"
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+                    "value_src": "default_prop"
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+                    "value_src": "default_prop"
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+            "inst_hier_path": "M9_codeur_i2s/mux2_0",
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+                    "value_src": "ip_prop"
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+            "inst_hier_path": "M9_codeur_i2s/reg_dec_24b_fd_0",
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+              "ref_name": "reg_dec_24b_fd",
+              "boundary_crc": "0x0"
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+                "parameters": {
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+                    "value_src": "user_prop"
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+                    "value_src": "default_prop"
+                  }
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+              },
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+            "inst_hier_path": "M9_codeur_i2s/util_vector_logic_0",
+            "parameters": {
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+            "inst_hier_path": "M9_codeur_i2s/xlconcat_0"
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+            "inst_hier_path": "M9_codeur_i2s/xlconstant_0"
+          },
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+            "xci_name": "design_1_xlslice_0_0",
+            "xci_path": "ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci",
+            "inst_hier_path": "M9_codeur_i2s/xlslice_0",
+            "parameters": {
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+            }
+          }
+        },
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+              "compteur_nbits_0/o_val_cpt",
+              "mef_cod_i2s_vsb_0/i_cpt_bits"
+            ]
+          },
+          "mef_cod_i2s_vsb_0_o_cpt_bit_reset": {
+            "ports": [
+              "mef_cod_i2s_vsb_0/o_cpt_bit_reset",
+              "compteur_nbits_0/reset"
+            ]
+          },
+          "mef_cod_i2s_vsb_0_o_bit_enable": {
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+              "mef_cod_i2s_vsb_0/o_bit_enable",
+              "compteur_nbits_0/i_en",
+              "reg_dec_24b_fd_0/i_en"
+            ]
+          },
+          "mux2_0_output": {
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+              "mux2_0/output0",
+              "reg_dec_24b_fd_0/i_dat_load"
+            ]
+          },
+          "util_vector_logic_0_Res": {
+            "ports": [
+              "util_vector_logic_0/Res",
+              "reg_dec_24b_fd_0/i_load"
+            ]
+          },
+          "mef_cod_i2s_vsb_0_o_load_left": {
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+              "mef_cod_i2s_vsb_0/o_load_left",
+              "util_vector_logic_0/Op1",
+              "xlconcat_0/In0"
+            ]
+          },
+          "mef_cod_i2s_vsb_0_o_load_right": {
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+              "mef_cod_i2s_vsb_0/o_load_right",
+              "util_vector_logic_0/Op2",
+              "xlconcat_0/In1"
+            ]
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+              "xlconcat_0/dout",
+              "mux2_0/sel"
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+              "mef_cod_i2s_vsb_0/i_lrc"
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+              "mux2_0/input1"
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+              "mux2_0/input2"
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+              "i_reset",
+              "mef_cod_i2s_vsb_0/i_reset",
+              "reg_dec_24b_fd_0/i_reset"
+            ]
+          },
+          "i_bclk_0_1": {
+            "ports": [
+              "i_bclk",
+              "compteur_nbits_0/clk",
+              "mef_cod_i2s_vsb_0/i_bclk",
+              "reg_dec_24b_fd_0/i_clk"
+            ]
+          },
+          "xlconstant_0_dout": {
+            "ports": [
+              "xlconstant_0/dout",
+              "reg_dec_24b_fd_0/i_dat_bit"
+            ]
+          },
+          "reg_dec_24b_fd_0_o_dat": {
+            "ports": [
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+              "xlslice_0/Din"
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+          },
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+              "o_dat"
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+        "inst_hier_path": "M10_conversion_affichage",
+        "reference_info": {
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+          "ref_name": "affhexPmodSSD_v3",
+          "boundary_crc": "0x0"
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+            "direction": "I",
+            "parameters": {
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+                "value_src": "constant"
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+                "value_src": "user_prop"
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+                "value_src": "default_prop"
+              }
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+          },
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+            "right": "0"
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+        "inst_hier_path": "M5_parametre_1",
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+          "ref_name": "calcul_param_1",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
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+            "parameters": {
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+                "value_src": "user_prop"
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+                "value_src": "default_prop"
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+                "value_src": "default_prop"
+              }
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+        "inst_hier_path": "M6_parametre_2",
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+          "ref_name": "calcul_param_2",
+          "boundary_crc": "0x0"
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+            "parameters": {
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+                "value_src": "user_prop"
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+                "value_src": "default_prop"
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+                "value_src": "default_prop"
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+        "inst_hier_path": "M7_parametre_3",
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+          "boundary_crc": "0x0"
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+            "parameters": {
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+                "value_src": "user_prop"
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+                "value_src": "default_prop"
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+                "value_src": "default_prop"
+              }
+            }
+          },
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+        "xci_name": "design_1_Multiplexeur_choix_fonction_0",
+        "xci_path": "ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xci",
+        "inst_hier_path": "Multiplexeur_choix_fonction",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "mux4",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "input0": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "input1": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "input2": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "input3": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "sel": {
+            "direction": "I",
+            "left": "1",
+            "right": "0"
+          },
+          "output0": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          }
+        }
+      },
+      "Multiplexeur_choix_parametre": {
+        "vlnv": "xilinx.com:module_ref:mux4:1.0",
+        "xci_name": "design_1_Multiplexeur_choix_parametre_0",
+        "xci_path": "ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xci",
+        "inst_hier_path": "Multiplexeur_choix_parametre",
+        "parameters": {
+          "input_length": {
+            "value": "8"
+          }
+        },
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "mux4",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "input0": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "input1": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "input2": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "input3": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "sel": {
+            "direction": "I",
+            "left": "1",
+            "right": "0"
+          },
+          "output0": {
+            "direction": "O",
+            "left": "7",
+            "right": "0"
+          }
+        }
+      },
+      "M4_fonction3": {
+        "vlnv": "xilinx.com:module_ref:sig_fct_3:1.0",
+        "xci_name": "design_1_M4_fonction3_0",
+        "xci_path": "ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xci",
+        "inst_hier_path": "M4_fonction3",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "sig_fct_3",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "i_ech": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "o_ech_fct": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          }
+        }
+      },
+      "M2_fonction_distortion_dure1": {
+        "vlnv": "xilinx.com:module_ref:sig_fct_sat_dure:1.0",
+        "xci_name": "design_1_M2_fonction_distortion_dure1_0",
+        "xci_path": "ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xci",
+        "inst_hier_path": "M2_fonction_distortion_dure1",
+        "parameters": {
+          "c_ech_u24_max": {
+            "value": "0x7FFFFF"
+          }
+        },
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "sig_fct_sat_dure",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "i_ech": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "o_ech_fct": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          }
+        }
+      },
+      "M3_fonction_distorsion_dure2": {
+        "vlnv": "xilinx.com:module_ref:sig_fct_sat_dure:1.0",
+        "xci_name": "design_1_M3_fonction_distorsion_dure2_0",
+        "xci_path": "ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xci",
+        "inst_hier_path": "M3_fonction_distorsion_dure2",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "sig_fct_sat_dure",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "i_ech": {
+            "direction": "I",
+            "left": "23",
+            "right": "0"
+          },
+          "o_ech_fct": {
+            "direction": "O",
+            "left": "23",
+            "right": "0"
+          }
+        }
+      },
+      "parametre_0": {
+        "vlnv": "xilinx.com:ip:xlconstant:1.1",
+        "xci_name": "design_1_parametre_0_0",
+        "xci_path": "ip/design_1_parametre_0_0/design_1_parametre_0_0.xci",
+        "inst_hier_path": "parametre_0",
+        "parameters": {
+          "CONST_VAL": {
+            "value": "0"
+          },
+          "CONST_WIDTH": {
+            "value": "8"
+          }
+        }
+      },
+      "M8_commande": {
+        "vlnv": "xilinx.com:module_ref:module_commande:1.0",
+        "xci_name": "design_1_M8_commande_0",
+        "xci_path": "ip/design_1_M8_commande_0/design_1_M8_commande_0.xci",
+        "inst_hier_path": "M8_commande",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "module_commande",
+          "boundary_crc": "0x0"
+        },
+        "ports": {
+          "clk": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "user_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "design_1_clk_100MHz",
+                "value_src": "default_prop"
+              }
+            }
+          },
+          "o_reset": {
+            "type": "rst",
+            "direction": "O"
+          },
+          "i_btn": {
+            "direction": "I",
+            "left": "3",
+            "right": "0"
+          },
+          "i_sw": {
+            "direction": "I",
+            "left": "3",
+            "right": "0"
+          },
+          "o_btn_cd": {
+            "direction": "O",
+            "left": "3",
+            "right": "0"
+          },
+          "o_selection_fct": {
+            "direction": "O",
+            "left": "1",
+            "right": "0"
+          },
+          "o_selection_par": {
+            "direction": "O",
+            "left": "1",
+            "right": "0"
+          }
+        }
+      }
+    },
+    "nets": {
+      "sig_fct_sat_dure_0_o_ech_fct": {
+        "ports": [
+          "M2_fonction_distortion_dure1/o_ech_fct",
+          "Multiplexeur_choix_fonction/input1"
+        ]
+      },
+      "sig_fct_sat_dure_1_o_ech_fct": {
+        "ports": [
+          "M3_fonction_distorsion_dure2/o_ech_fct",
+          "Multiplexeur_choix_fonction/input2"
+        ]
+      },
+      "sig_fct_3_0_o_ech_fct": {
+        "ports": [
+          "M4_fonction3/o_ech_fct",
+          "Multiplexeur_choix_fonction/input3"
+        ]
+      },
+      "module_commande_0_o_selection_fct": {
+        "ports": [
+          "M8_commande/o_selection_fct",
+          "o_sel_fct",
+          "Multiplexeur_choix_fonction/sel"
+        ]
+      },
+      "calcul_param_1_0_o_param": {
+        "ports": [
+          "M5_parametre_1/o_param",
+          "Multiplexeur_choix_parametre/input1"
+        ]
+      },
+      "calcul_param_2_0_o_param": {
+        "ports": [
+          "M6_parametre_2/o_param",
+          "Multiplexeur_choix_parametre/input2"
+        ]
+      },
+      "calcul_param_3_0_o_param": {
+        "ports": [
+          "M7_parametre_3/o_param",
+          "Multiplexeur_choix_parametre/input3"
+        ]
+      },
+      "xlconstant_0_dout": {
+        "ports": [
+          "parametre_0/dout",
+          "Multiplexeur_choix_parametre/input0"
+        ]
+      },
+      "decodeur_i2s_o_str_dat": {
+        "ports": [
+          "M1_decodeur_i2s/o_str_dat",
+          "M5_parametre_1/i_en",
+          "M6_parametre_2/i_en",
+          "M7_parametre_3/i_en"
+        ]
+      },
+      "clk_1": {
+        "ports": [
+          "clk_100MHz",
+          "M1_decodeur_i2s/clk",
+          "M9_codeur_i2s/i_bclk",
+          "M10_conversion_affichage/clk",
+          "M5_parametre_1/i_bclk",
+          "M6_parametre_2/i_bclk",
+          "M7_parametre_3/i_bclk",
+          "M8_commande/clk"
+        ]
+      },
+      "i_data_1": {
+        "ports": [
+          "i_recdat",
+          "M1_decodeur_i2s/i_data"
+        ]
+      },
+      "i_lrc_1": {
+        "ports": [
+          "i_lrc",
+          "M1_decodeur_i2s/i_lrc",
+          "M9_codeur_i2s/i_lrc"
+        ]
+      },
+      "mux4_1_output": {
+        "ports": [
+          "Multiplexeur_choix_parametre/output0",
+          "o_param",
+          "M10_conversion_affichage/DA"
+        ]
+      },
+      "i_btn_1": {
+        "ports": [
+          "i_btn",
+          "M8_commande/i_btn"
+        ]
+      },
+      "i_sw_1": {
+        "ports": [
+          "i_sw",
+          "M8_commande/i_sw"
+        ]
+      },
+      "i_dat_left_1": {
+        "ports": [
+          "M1_decodeur_i2s/o_dat_left",
+          "M9_codeur_i2s/i_dat_left"
+        ]
+      },
+      "i_dat_right_1": {
+        "ports": [
+          "Multiplexeur_choix_fonction/output0",
+          "M9_codeur_i2s/i_dat_right",
+          "M5_parametre_1/i_ech",
+          "M6_parametre_2/i_ech",
+          "M7_parametre_3/i_ech"
+        ]
+      },
+      "decodeur_i2s_o_dat_right": {
+        "ports": [
+          "M1_decodeur_i2s/o_dat_right",
+          "Multiplexeur_choix_fonction/input0",
+          "M4_fonction3/i_ech",
+          "M2_fonction_distortion_dure1/i_ech",
+          "M3_fonction_distorsion_dure2/i_ech"
+        ]
+      },
+      "M8_commande_o_selection_par": {
+        "ports": [
+          "M8_commande/o_selection_par",
+          "o_sel_par",
+          "Multiplexeur_choix_parametre/sel"
+        ]
+      },
+      "M9_codeur_i2s_o_dat": {
+        "ports": [
+          "M9_codeur_i2s/o_dat",
+          "o_pbdat"
+        ]
+      },
+      "M10_conversion_affichage_JPmod": {
+        "ports": [
+          "M10_conversion_affichage/JPmod",
+          "JPmod"
+        ]
+      },
+      "i_reset_1": {
+        "ports": [
+          "M8_commande/o_reset",
+          "M1_decodeur_i2s/i_reset",
+          "M9_codeur_i2s/i_reset",
+          "M10_conversion_affichage/reset",
+          "M5_parametre_1/i_reset",
+          "M6_parametre_2/i_reset",
+          "M7_parametre_3/i_reset"
+        ]
+      },
+      "M8_commande_o_btn_cd": {
+        "ports": [
+          "M8_commande/o_btn_cd",
+          "M10_conversion_affichage/i_btn"
+        ]
+      }
+    },
+    "comments": {
+      "/": {
+        "comment_1": "Modules à modifier:\nMEF_decodeur_i2s (dans M1_decodeur_i2s)\nM5_parametre_1\nM6_parametre_2\nM8_commande\nPour plus de clarté, vous pouvez cacher les fils pour les horloges\net les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).\n"
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xci
new file mode 100644
index 0000000..8dde12c
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0/design_1_M10_conversion_affichage_0.xci
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_M10_conversion_affichage_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="affhexPmodSSD_v3" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.const_CLK_Hz">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_M10_conversion_affichage_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.const_CLK_Hz">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M10_conversion_affichage_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
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diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xci
new file mode 100644
index 0000000..0cbf235
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M2_fonction_distortion_dure1_0/design_1_M2_fonction_distortion_dure1_0.xci
@@ -0,0 +1,46 @@
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+  <spirit:vendor>xilinx.com</spirit:vendor>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
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diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xci
new file mode 100644
index 0000000..9b05ad7
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M3_fonction_distorsion_dure2_0/design_1_M3_fonction_distorsion_dure2_0.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ech_u24_max">0x1FFFFF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xci
new file mode 100644
index 0000000..cc1687d
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M4_fonction3_0/design_1_M4_fonction3_0.xci
@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M4_fonction3_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
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diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xci
new file mode 100644
index 0000000..a07651e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M5_parametre_1_0/design_1_M5_parametre_1_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xci
new file mode 100644
index 0000000..c9c20b2
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0/design_1_M6_parametre_2_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_M6_parametre_2_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="calcul_param_2" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_M6_parametre_2_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M6_parametre_2_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_ech&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_param&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xci
new file mode 100644
index 0000000..f884a26
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0/design_1_M7_parametre_3_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_M7_parametre_3_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="calcul_param_3" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_M7_parametre_3_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M7_parametre_3_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_ech&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_param&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xci
new file mode 100644
index 0000000..a541e6f
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_M8_commande_0/design_1_M8_commande_0.xci
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_M8_commande_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="module_commande" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.mode_simulation">&quot;0&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbtn">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_M8_commande_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_simulation">&quot;0&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbtn">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_M8_commande_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_btn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_sw&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_btn_cd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_selection_fct&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_selection_par&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;o_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_
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+pe&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xci
new file mode 100644
index 0000000..c60358d
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0/design_1_MEF_decodeur_i2s_0.xci
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_MEF_decodeur_i2s_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mef_decod_i2s_v1b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_MEF_decodeur_i2s_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_MEF_decodeur_i2s_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_lrc&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_cpt_bits&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_bit_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_left&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_right&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_str_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_cpt_bit_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;defa
+ult&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;o_cpt_bit_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_cpt_bit_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xci
new file mode 100644
index 0000000..b9556f5
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0/design_1_Multiplexeur_choix_fonction_0.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_Multiplexeur_choix_fonction_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux4" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_Multiplexeur_choix_fonction_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_fonction_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xci
new file mode 100644
index 0000000..db1485a
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0/design_1_Multiplexeur_choix_parametre_0.xci
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_Multiplexeur_choix_parametre_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux4" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_Multiplexeur_choix_parametre_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_Multiplexeur_choix_parametre_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.input_length" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xci
new file mode 100644
index 0000000..4ae225e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0/design_1_affhexPmodSSD_v3_0_0.xci
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_affhexPmodSSD_v3_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="affhexPmodSSD_v3" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.const_CLK_Hz">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_affhexPmodSSD_v3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.const_CLK_Hz">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_affhexPmodSSD_v3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DA&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_btn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;JPmod&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_
+RESET&quot;:[{&quot;value&quot;:&quot;reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xci
new file mode 100644
index 0000000..9c76962
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0/design_1_calcul_param_1_0_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_calcul_param_1_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="calcul_param_1" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_calcul_param_1_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_1_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_ech&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_param&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xci
new file mode 100644
index 0000000..793a998
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0/design_1_calcul_param_2_0_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_calcul_param_2_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="calcul_param_2" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_calcul_param_2_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_2_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_ech&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_param&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xci
new file mode 100644
index 0000000..7caf920
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0/design_1_calcul_param_3_0_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_calcul_param_3_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="calcul_param_3" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_calcul_param_3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_calcul_param_3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_ech&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_param&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xci
new file mode 100644
index 0000000..0ec6ae1
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_7bits_0/design_1_compteur_7bits_0.xci
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_compteur_7bits_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="compteur_nbits" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_compteur_7bits_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_7bits_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_val_cpt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_per
+mission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xci
new file mode 100644
index 0000000..b2472a5
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0/design_1_compteur_nbits_0_0.xci
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_compteur_nbits_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="compteur_nbits" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_compteur_nbits_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_val_cpt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_per
+mission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xci
new file mode 100644
index 0000000..9a8fafe
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1/design_1_compteur_nbits_0_0.xci
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_compteur_nbits_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="compteur_nbits" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_compteur_nbits_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_val_cpt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_per
+mission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xci
new file mode 100644
index 0000000..59ac91e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1/design_1_compteur_nbits_0_1.xci
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_compteur_nbits_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="compteur_nbits" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_compteur_nbits_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbits">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_compteur_nbits_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.nbits" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_val_cpt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_per
+mission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xci
new file mode 100644
index 0000000..7bc3a68
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0/design_1_mef_cod_i2s_vsb_0_0.xci
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mef_cod_i2s_vsb_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mef_cod_i2s_vsb" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mef_cod_i2s_vsb_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_lrc&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_cpt_bits&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_bit_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_left&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_right&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_cpt_bit_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{
+&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;o_cpt_bit_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_cpt_bit_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci
new file mode 100644
index 0000000..6a2380a
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1/design_1_mef_cod_i2s_vsb_0_0.xci
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mef_cod_i2s_vsb_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mef_cod_i2s_vsb" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mef_cod_i2s_vsb_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_cod_i2s_vsb_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_lrc&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_cpt_bits&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_bit_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_left&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_right&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_cpt_bit_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{
+&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;o_cpt_bit_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_cpt_bit_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xci
new file mode 100644
index 0000000..71d44ba
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0/design_1_mef_decod_i2s_v1b_0_0.xci
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mef_decod_i2s_v1b_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mef_decod_i2s_v1b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mef_decod_i2s_v1b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mef_decod_i2s_v1b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_CPT_BIT_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_bclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_lrc&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_cpt_bits&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;6&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_bit_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_left&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_load_right&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_str_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_cpt_bit_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;defa
+ult&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;o_cpt_bit_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_cpt_bit_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xci
new file mode 100644
index 0000000..a7debdd
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_module_commande_0_0/design_1_module_commande_0_0.xci
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_module_commande_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="module_commande" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.mode_simulation">&quot;0&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nbtn">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_module_commande_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_simulation">&quot;0&quot;</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.nbtn">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_module_commande_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.O_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_btn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_sw&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_btn_cd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_selection_fct&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_selection_par&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;o_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;o_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_
+left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_ty
+pe&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xci
new file mode 100644
index 0000000..bdb66d2
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0/design_1_mux2_0_0.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mux2_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux2" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mux2_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xci
new file mode 100644
index 0000000..2890fd2
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux2_0_0_1/design_1_mux2_0_0.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mux2_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux2" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mux2_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux2_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xci
new file mode 100644
index 0000000..e6e7a01
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_0/design_1_mux4_0_0.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mux4_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux4" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mux4_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xci
new file mode 100644
index 0000000..f1ec515
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_mux4_0_1/design_1_mux4_0_1.xci
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_mux4_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="mux4" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.input_length">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_mux4_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.input_length">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_mux4_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.input_length" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xci
new file mode 100644
index 0000000..ce77c2f
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_parametre_0_0/design_1_parametre_0_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_parametre_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_parametre_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_parametre_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xci
new file mode 100644
index 0000000..32f1351
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_0/design_1_reg_24b_0_0.xci
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_reg_24b_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_reg_24b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;
+:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xci
new file mode 100644
index 0000000..50cd924
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_24b_0_1/design_1_reg_24b_0_1.xci
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_reg_24b_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_reg_24b_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_24b_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;
+:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xci
new file mode 100644
index 0000000..584e7cf
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0/design_1_reg_dec_24b_0_0.xci
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_reg_dec_24b_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_dec_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_reg_dec_24b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_bit&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
+gical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xci
new file mode 100644
index 0000000..6ef5855
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0/design_1_reg_dec_24b_fd_0_0.xci
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_reg_dec_24b_fd_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_dec_24b_fd" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_reg_dec_24b_fd_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_bit&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
+gical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xci
new file mode 100644
index 0000000..7c7c2ad
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1/design_1_reg_dec_24b_fd_0_0.xci
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_reg_dec_24b_fd_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_dec_24b_fd" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_reg_dec_24b_fd_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_reg_dec_24b_fd_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_bit&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
+gical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xci
new file mode 100644
index 0000000..bfa06f4
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0/design_1_registre_24bits_droite_0.xci
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_registre_24bits_droite_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_registre_24bits_droite_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_droite_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;
+:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xci
new file mode 100644
index 0000000..f99e74e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0/design_1_registre_24bits_gauche_0.xci
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_registre_24bits_gauche_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_registre_24bits_gauche_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_24bits_gauche_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;
+:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xci
new file mode 100644
index 0000000..9bba8b7
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0/design_1_registre_decalage_24bits_0.xci
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_registre_decalage_24bits_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="reg_dec_24b" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_registre_decalage_24bits_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_registre_decalage_24bits_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.I_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;i_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_bit&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;i_dat_load&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;o_dat&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;23&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;i_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;i_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;lo
+gical_right&quot;:&quot;0&quot;}}},&quot;i_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;i_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;design_1_clk_100MHz&quot;},{&quot;value_src&quot;:&quot;default_prop&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd_and_user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;i_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xci
new file mode 100644
index 0000000..1a52218
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0/design_1_sig_fct_3_0_0.xci
@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_sig_fct_3_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="sig_fct_3" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_sig_fct_3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_3_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xci
new file mode 100644
index 0000000..83a9a1c
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0/design_1_sig_fct_sat_dure_0_0.xci
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="sig_fct_sat_dure" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_sig_fct_sat_dure_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ech_u24_max">0x7FFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_ech_u24_max" xilinx:valueSource="user"/>
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+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xci
new file mode 100644
index 0000000..a97a128
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1/design_1_sig_fct_sat_dure_0_1.xci
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
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+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_sig_fct_sat_dure_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="sig_fct_sat_dure" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ech_u24_max">0x1FFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_sig_fct_sat_dure_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ech_u24_max">0x1FFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_sig_fct_sat_dure_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci
new file mode 100644
index 0000000..b6083b7
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
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+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_util_vector_logic_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPERATION">or</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_util_vector_logic_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOGO_FILE">data/sym_orgate.png</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_OPERATION" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SIZE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOGO_FILE" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xci
new file mode 100644
index 0000000..ca99ab6
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1/design_1_util_vector_logic_0_0.xci
@@ -0,0 +1,50 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
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+      <spirit:instanceName>design_1_util_vector_logic_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_util_vector_logic_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOGO_FILE">data/sym_orgate.png</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_OPERATION" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SIZE" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci
new file mode 100644
index 0000000..d9c6695
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
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+      <spirit:instanceName>design_1_xlconcat_0_0</spirit:instanceName>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN94_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN95_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN96_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN97_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN98_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN99_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN9_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dout_width" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xci
new file mode 100644
index 0000000..72ef507
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconcat_0_0_1/design_1_xlconcat_0_0.xci
@@ -0,0 +1,432 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconcat_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconcat" spirit:version="2.1"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN80_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN81_WIDTH" xilinx:valuePermission="bd_and_user"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN83_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN84_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN85_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN86_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN87_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN88_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN89_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN8_WIDTH" xilinx:valuePermission="bd_and_user"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN91_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN92_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN93_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN94_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN95_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN96_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN97_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN98_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN99_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN9_WIDTH" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dout_width" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci
new file mode 100644
index 0000000..f172a8e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xci
new file mode 100644
index 0000000..8085194
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1/design_1_xlconstant_0_0.xci
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xci
new file mode 100644
index 0000000..1f2402d
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1/design_1_xlconstant_0_1.xci
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xci
new file mode 100644
index 0000000..20d8e64
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1/design_1_xlconstant_0_1.xci
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_1_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xci
new file mode 100644
index 0000000..d44584f
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_2/design_1_xlconstant_0_2.xci
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_2</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xci
new file mode 100644
index 0000000..94d4ba3
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_3/design_1_xlconstant_0_3.xci
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_0_3</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x000001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_0_3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci
new file mode 100644
index 0000000..5821b63
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_1_0/design_1_xlconstant_1_0.xci
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlconstant_1_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x000001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlconstant_1_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlconstant_1_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci
new file mode 100644
index 0000000..0bf5c35
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlslice_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlslice" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_FROM">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_TO">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlslice_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_FROM">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_TO">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:zybo-z7-10:part0:1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_FROM" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_TO" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DOUT_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci
new file mode 100644
index 0000000..cc800da
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1/design_1_xlslice_0_0.xci
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>design_1_xlslice_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlslice" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_FROM">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_TO">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIN_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_xlslice_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_FROM">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_TO">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_WIDTH">24</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../pb_logique_seq.gen/sources_1/bd/design_1/ip/design_1_xlslice_0_0_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_FROM" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_TO" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DIN_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DOUT_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
new file mode 100644
index 0000000..e871169
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
@@ -0,0 +1,81 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_Layers":"/clk_1:true|",
+   "Default View_ScaleFactor":"0.90984",
+   "Default View_TopLeft":"97,125",
+   "Display-PortTypeClock":"true",
+   "ExpandedHierarchyInLayout":"",
+   "comment_1":"Modules à modifier:
+MEF_decodeur_i2s (dans M1_decodeur_i2s)
+M5_parametre_1
+M6_parametre_2
+M8_commande
+Pour plus de clarté, vous pouvez cacher les fils pour les horloges
+et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).
+",
+   "commentid":"comment_1|",
+   "font_comment_1":"14",
+   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port i_recdat -pg 1 -lvl 0 -x -140 -y 340 -defaultsOSRD
+preplace port i_lrc -pg 1 -lvl 0 -x -140 -y 360 -defaultsOSRD
+preplace port clk_100MHz -pg 1 -lvl 0 -x -140 -y 380 -defaultsOSRD
+preplace portBus i_btn -pg 1 -lvl 0 -x -140 -y 730 -defaultsOSRD
+preplace portBus i_sw -pg 1 -lvl 0 -x -140 -y 750 -defaultsOSRD
+preplace portBus o_pbdat -pg 1 -lvl 7 -x 2150 -y 570 -defaultsOSRD
+preplace portBus JPmod -pg 1 -lvl 7 -x 2150 -y 270 -defaultsOSRD
+preplace portBus o_param -pg 1 -lvl 7 -x 2150 -y 120 -defaultsOSRD
+preplace portBus o_sel_par -pg 1 -lvl 7 -x 2150 -y 720 -defaultsOSRD
+preplace portBus o_sel_fct -pg 1 -lvl 7 -x 2150 -y 700 -defaultsOSRD
+preplace inst M1_decodeur_i2s -pg 1 -lvl 1 -x 70 -y 350 -defaultsOSRD
+preplace inst M9_codeur_i2s -pg 1 -lvl 1 -x 70 -y 570 -defaultsOSRD
+preplace inst M10_conversion_affichage -pg 1 -lvl 6 -x 1670 -y 270 -defaultsOSRD
+preplace inst M5_parametre_1 -pg 1 -lvl 4 -x 1040 -y 160 -defaultsOSRD
+preplace inst M6_parametre_2 -pg 1 -lvl 4 -x 1040 -y 320 -defaultsOSRD
+preplace inst M7_parametre_3 -pg 1 -lvl 4 -x 1040 -y 480 -defaultsOSRD
+preplace inst Multiplexeur_choix_fonction -pg 1 -lvl 3 -x 710 -y 270 -defaultsOSRD
+preplace inst Multiplexeur_choix_parametre -pg 1 -lvl 5 -x 1360 -y 280 -defaultsOSRD
+preplace inst M4_fonction3 -pg 1 -lvl 2 -x 390 -y 380 -defaultsOSRD
+preplace inst M2_fonction_distortion_dure1 -pg 1 -lvl 2 -x 390 -y 180 -defaultsOSRD
+preplace inst M3_fonction_distorsion_dure2 -pg 1 -lvl 2 -x 390 -y 280 -defaultsOSRD
+preplace inst parametre_0 -pg 1 -lvl 4 -x 1040 -y 30 -defaultsOSRD
+preplace inst M8_commande -pg 1 -lvl 2 -x 390 -y 730 -defaultsOSRD
+preplace netloc sig_fct_sat_dure_0_o_ech_fct 1 2 1 540 180n
+preplace netloc sig_fct_sat_dure_1_o_ech_fct 1 2 1 550 270n
+preplace netloc sig_fct_3_0_o_ech_fct 1 2 1 540 290n
+preplace netloc module_commande_0_o_selection_fct 1 2 5 550 700 N 700 N 700 N 700 N
+preplace netloc calcul_param_1_0_o_param 1 4 1 1180 160n
+preplace netloc calcul_param_2_0_o_param 1 4 1 1180 280n
+preplace netloc calcul_param_3_0_o_param 1 4 1 1190 300n
+preplace netloc xlconstant_0_dout 1 4 1 1200 30n
+preplace netloc decodeur_i2s_o_str_dat 1 1 3 210J 110 NJ 110 880
+preplace netloc clk_1 1 0 6 -110 450 210 450 NJ 450 870 590 1210J 560 1500
+preplace netloc i_data_1 1 0 1 NJ 340
+preplace netloc i_lrc_1 1 0 1 -120 360n
+preplace netloc mux4_1_output 1 5 2 1510 120 N
+preplace netloc i_btn_1 1 0 2 NJ 730 NJ
+preplace netloc i_sw_1 1 0 2 NJ 750 NJ
+preplace netloc i_dat_left_1 1 0 2 -90 260 200J
+preplace netloc i_dat_right_1 1 0 4 -80 460 N 460 N 460 900
+preplace netloc decodeur_i2s_o_dat_right 1 1 2 220 120 550
+preplace netloc M8_commande_o_selection_par 1 2 5 N 760 N 760 1200 720 N 720 N
+preplace netloc M9_codeur_i2s_o_dat 1 1 6 N 570 N 570 860 580 N 580 1530 570 N
+preplace netloc M10_conversion_affichage_JPmod 1 6 1 N 270
+preplace netloc i_reset_1 1 0 6 -100 470 NJ 470 540J 470 890 570 N 570 1520
+preplace netloc M8_commande_o_btn_cd 1 2 4 N 720 N 720 1180 550 1510
+preplace cgraphic comment_1 place top 0 20 textcolor 4 linecolor 3
+levelinfo -pg 1 -140 70 390 710 1040 1360 1670 2150
+pagesize -pg 1 -db -bbox -sgen -280 -20 2300 860
+",
+   "linktoobj_comment_1":"",
+   "linktotype_comment_1":"bd_design"
+}
+{
+   """"""""""""""""""""""""""""da_clkrst_cnt"""""""""""""""""""""""""""":"1"
+}
+{
+   "/comment_1":"comment_1",
+   "/comment_2":"comment_2",
+   "/comment_3":"comment_0",
+   "/comment_4":"comment_3"
+}
\ No newline at end of file
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_72e80fe5.ui b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_72e80fe5.ui
new file mode 100644
index 0000000..7bffbd6
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_72e80fe5.ui
@@ -0,0 +1,42 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.651547",
+   "Default View_TopLeft":"-152,-117",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
+#  -string -flagsOSRD
+preplace port i_lrc -pg 1 -lvl 0 -x 0 -y 370 -defaultsOSRD
+preplace port i_reset -pg 1 -lvl 0 -x 0 -y 350 -defaultsOSRD
+preplace port i_bclk -pg 1 -lvl 0 -x 0 -y 390 -defaultsOSRD
+preplace portBus i_dat_left -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
+preplace portBus i_dat_right -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
+preplace portBus o_dat -pg 1 -lvl 7 -x 1620 -y 350 -defaultsOSRD
+preplace inst mef_cod_i2s_vsb_0 -pg 1 -lvl 2 -x 440 -y 420 -defaultsOSRD
+preplace inst compteur_nbits_0 -pg 1 -lvl 1 -x 150 -y 450 -defaultsOSRD
+preplace inst reg_dec_24b_fd_0 -pg 1 -lvl 5 -x 1250 -y 350 -defaultsOSRD
+preplace inst mux2_0 -pg 1 -lvl 4 -x 940 -y 220 -defaultsOSRD
+preplace inst util_vector_logic_0 -pg 1 -lvl 4 -x 940 -y 70 -defaultsOSRD
+preplace inst xlconcat_0 -pg 1 -lvl 3 -x 700 -y 150 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 4 -x 940 -y 380 -defaultsOSRD
+preplace inst xlslice_0 -pg 1 -lvl 6 -x 1500 -y 350 -defaultsOSRD
+preplace netloc compteur_nbits_0_o_val_cpt 1 1 1 N 450
+preplace netloc mef_cod_i2s_vsb_0_o_cpt_bit_reset 1 0 3 30 530 NJ 530 600
+preplace netloc mef_cod_i2s_vsb_0_o_bit_enable 1 0 5 30 310 NJ 310 590 310 NJ 310 1090
+preplace netloc mux2_0_output 1 4 1 1100 220n
+preplace netloc util_vector_logic_0_Res 1 4 1 1110 70n
+preplace netloc mef_cod_i2s_vsb_0_o_load_left 1 2 2 600 60 NJ
+preplace netloc mef_cod_i2s_vsb_0_o_load_right 1 2 2 610 80 NJ
+preplace netloc xlconcat_0_dout 1 3 1 790 150n
+preplace netloc i_lrc_0_1 1 0 2 NJ 370 270J
+preplace netloc input1_0_1 1 0 4 NJ 220 NJ 220 NJ 220 NJ
+preplace netloc input2_0_1 1 0 4 NJ 240 NJ 240 NJ 240 NJ
+preplace netloc i_reset_0_1 1 0 5 NJ 350 290 320 NJ 320 NJ 320 NJ
+preplace netloc i_bclk_0_1 1 0 5 20 360 280 300 NJ 300 NJ 300 NJ
+preplace netloc xlconstant_0_dout 1 4 1 NJ 380
+preplace netloc reg_dec_24b_fd_0_o_dat 1 5 1 NJ 350
+preplace netloc xlslice_0_Dout 1 6 1 NJ 350
+levelinfo -pg 1 0 150 440 700 940 1250 1500 1620
+pagesize -pg 1 -db -bbox -sgen -160 0 1740 540
+"
+}
+
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_a93fd001.ui b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_a93fd001.ui
new file mode 100644
index 0000000..4782fda
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_a93fd001.ui
@@ -0,0 +1,46 @@
+{
+   "/comment_1":"comment_0",
+   "ActiveEmotionalView":"Default View",
+   "Default View_Layers":"/M1_decodeur_i2s/clk_1:true|/M1_decodeur_i2s/mef_decod_i2s_v1b_0_o_cpt_bit_reset:true|/M1_decodeur_i2s/i_reset_1:true|",
+   "Default View_ScaleFactor":"0.812903",
+   "Default View_TopLeft":"-105,60",
+   "Display-PortTypeClock":"true",
+   "Display-PortTypeOthers":"true",
+   "Display-PortTypeReset":"true",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
+#  -string -flagsOSRD
+preplace port o_str_dat -pg 1 -lvl 4 -x 940 -y 180 -defaultsOSRD
+preplace port clk -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
+preplace port i_data -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
+preplace port i_lrc -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD
+preplace port i_reset -pg 1 -lvl 0 -x 0 -y 440 -defaultsOSRD
+preplace portBus o_dat_left -pg 1 -lvl 4 -x 940 -y 300 -defaultsOSRD
+preplace portBus o_dat_right -pg 1 -lvl 4 -x 940 -y 460 -defaultsOSRD
+preplace inst compteur_7bits -pg 1 -lvl 1 -x 160 -y 360 -defaultsOSRD
+preplace inst MEF_decodeur_i2s -pg 1 -lvl 2 -x 460 -y 160 -defaultsOSRD
+preplace inst registre_24bits_droite -pg 1 -lvl 3 -x 790 -y 460 -defaultsOSRD
+preplace inst registre_24bits_gauche -pg 1 -lvl 3 -x 790 -y 300 -defaultsOSRD
+preplace inst registre_decalage_24bits -pg 1 -lvl 2 -x 460 -y 510 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 1 -x 160 -y 500 -defaultsOSRD
+preplace inst xlconstant_1 -pg 1 -lvl 1 -x 160 -y 620 -defaultsOSRD
+preplace netloc reg_dec_24b_0_o_dat 1 2 1 650 330n
+preplace netloc mef_decod_i2s_v1b_0_o_load_left 1 2 1 650 140n
+preplace netloc mef_decod_i2s_v1b_0_o_load_right 1 2 1 630 160n
+preplace netloc mef_decod_i2s_v1b_0_o_str_dat 1 2 2 NJ 180 NJ
+preplace netloc reg_24b_1_o_dat 1 3 1 NJ 300
+preplace netloc reg_24b_0_o_dat 1 3 1 NJ 460
+preplace netloc clk_1 1 0 3 20 270 300 270 660
+preplace netloc mef_decod_i2s_v1b_0_o_cpt_bit_reset 1 0 3 30 260 NJ 260 610
+preplace netloc mef_decod_i2s_v1b_0_o_bit_enable 1 0 3 40 280 280 280 620
+preplace netloc i_data_1 1 0 2 NJ 560 290J
+preplace netloc i_lrc_1 1 0 2 NJ 170 NJ
+preplace netloc compteur_nbits_0_o_val_cpt 1 1 1 290 190n
+preplace netloc i_reset_1 1 0 3 NJ 440 310 290 640
+preplace netloc xlconstant_0_dout 1 1 1 NJ 500
+preplace netloc xlconstant_1_dout 1 1 1 310J 560n
+levelinfo -pg 1 0 160 460 790 940
+pagesize -pg 1 -db -bbox -sgen -100 0 1100 680
+"
+}
+0
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_ab1f8e66.ui b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_ab1f8e66.ui
new file mode 100644
index 0000000..949814f
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_ab1f8e66.ui
@@ -0,0 +1,38 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.82623",
+   "Default View_TopLeft":"-531,-589",
+   "ExpandedHierarchyInLayout":"",
+   "commentid":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
+#  -string -flagsOSRD
+preplace port o_str_dat -pg 1 -lvl 3 -x 700 -y -480 -defaultsOSRD
+preplace port clk -pg 1 -lvl 0 -x -350 -y -520 -defaultsOSRD
+preplace port i_data -pg 1 -lvl 0 -x -350 -y -60 -defaultsOSRD
+preplace port i_lrc -pg 1 -lvl 0 -x -350 -y -480 -defaultsOSRD
+preplace port i_reset -pg 1 -lvl 0 -x -350 -y -500 -defaultsOSRD
+preplace portBus o_dat_left -pg 1 -lvl 3 -x 700 -y -390 -defaultsOSRD
+preplace portBus o_dat_right -pg 1 -lvl 3 -x 700 -y -230 -defaultsOSRD
+preplace inst MEF_decodeur_i2s -pg 1 -lvl 1 -x -140 -y -490 -defaultsOSRD
+preplace inst compteur_7bits -pg 1 -lvl 1 -x -140 -y -280 -defaultsOSRD
+preplace inst registre_decalage_24bits -pg 1 -lvl 1 -x -140 -y -90 -defaultsOSRD
+preplace inst registre_24bits_gauche -pg 1 -lvl 2 -x 420 -y -390 -defaultsOSRD
+preplace inst registre_24bits_droite -pg 1 -lvl 2 -x 420 -y -230 -defaultsOSRD
+preplace netloc reg_dec_24b_0_o_dat 1 1 1 60 -360n
+preplace netloc mef_decod_i2s_v1b_0_o_load_left 1 1 1 60 -510n
+preplace netloc mef_decod_i2s_v1b_0_o_load_right 1 1 1 40 -490n
+preplace netloc mef_decod_i2s_v1b_0_o_str_dat 1 1 2 50J -480 NJ
+preplace netloc reg_24b_1_o_dat 1 2 1 NJ -390
+preplace netloc reg_24b_0_o_dat 1 2 1 NJ -230
+preplace netloc clk_1 1 0 2 -320 -370 70
+preplace netloc mef_decod_i2s_v1b_0_o_cpt_bit_reset 1 0 2 -310 -360 20
+preplace netloc mef_decod_i2s_v1b_0_o_bit_enable 1 0 2 -300 -200 30
+preplace netloc i_data_1 1 0 1 NJ -60
+preplace netloc i_lrc_1 1 0 1 NJ -480
+preplace netloc compteur_nbits_0_o_val_cpt 1 0 2 -300 -380 10
+preplace netloc i_reset_1 1 0 2 -330 -390 80
+levelinfo -pg 1 -350 -140 420 700
+pagesize -pg 1 -db -bbox -sgen -450 -590 860 200
+"
+}
+0
diff --git a/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_c2b8c4f8.ui b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_c2b8c4f8.ui
new file mode 100644
index 0000000..ea876df
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/bd/design_1/ui/bd_c2b8c4f8.ui
@@ -0,0 +1,46 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_Layers":"/M9_codeur_i2s/i_bclk_0_1:true|/M9_codeur_i2s/mef_cod_i2s_vsb_0_o_cpt_bit_reset:true|/M9_codeur_i2s/i_reset_0_1:true|",
+   "Default View_ScaleFactor":"0.821352",
+   "Default View_TopLeft":"-172,-140",
+   "Display-PortTypeClock":"true",
+   "Display-PortTypeOthers":"true",
+   "Display-PortTypeReset":"true",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
+#  -string -flagsOSRD
+preplace port i_lrc -pg 1 -lvl 0 -x -20 -y 220 -defaultsOSRD
+preplace port i_reset -pg 1 -lvl 0 -x -20 -y 40 -defaultsOSRD
+preplace port i_bclk -pg 1 -lvl 0 -x -20 -y 20 -defaultsOSRD
+preplace portBus i_dat_left -pg 1 -lvl 0 -x -20 -y 80 -defaultsOSRD
+preplace portBus i_dat_right -pg 1 -lvl 0 -x -20 -y 100 -defaultsOSRD
+preplace portBus o_dat -pg 1 -lvl 7 -x 1680 -y 220 -defaultsOSRD
+preplace inst compteur_nbits_0 -pg 1 -lvl 1 -x 140 -y 300 -defaultsOSRD
+preplace inst mef_cod_i2s_vsb_0 -pg 1 -lvl 2 -x 430 -y 270 -defaultsOSRD
+preplace inst mux2_0 -pg 1 -lvl 4 -x 960 -y 80 -defaultsOSRD
+preplace inst reg_dec_24b_fd_0 -pg 1 -lvl 5 -x 1290 -y 220 -defaultsOSRD
+preplace inst util_vector_logic_0 -pg 1 -lvl 4 -x 960 -y 210 -defaultsOSRD
+preplace inst xlconcat_0 -pg 1 -lvl 3 -x 700 -y 270 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 4 -x 960 -y 400 -defaultsOSRD
+preplace inst xlslice_0 -pg 1 -lvl 6 -x 1550 -y 220 -defaultsOSRD
+preplace netloc compteur_nbits_0_o_val_cpt 1 1 1 NJ 300
+preplace netloc mef_cod_i2s_vsb_0_o_cpt_bit_reset 1 0 3 20 400 NJ 400 580
+preplace netloc mef_cod_i2s_vsb_0_o_bit_enable 1 0 5 10 390 NJ 390 590 340 790J 330 1140
+preplace netloc mux2_0_output 1 4 1 1120 80n
+preplace netloc util_vector_logic_0_Res 1 4 1 N 210
+preplace netloc mef_cod_i2s_vsb_0_o_load_left 1 2 2 610 200 N
+preplace netloc mef_cod_i2s_vsb_0_o_load_right 1 2 2 600 190 800
+preplace netloc xlconcat_0_dout 1 3 1 790 60n
+preplace netloc i_lrc_0_1 1 0 2 NJ 220 260J
+preplace netloc input1_0_1 1 0 4 NJ 80 NJ 80 NJ 80 NJ
+preplace netloc input2_0_1 1 0 4 NJ 100 NJ 100 NJ 100 NJ
+preplace netloc i_reset_0_1 1 0 5 NJ 40 270 360 NJ 360 810J 340 1130
+preplace netloc i_bclk_0_1 1 0 5 0 380 280 370 NJ 370 800J 320 1110
+preplace netloc xlconstant_0_dout 1 4 1 1150 250n
+preplace netloc reg_dec_24b_fd_0_o_dat 1 5 1 NJ 220
+preplace netloc xlslice_0_Dout 1 6 1 NJ 220
+levelinfo -pg 1 -20 140 430 700 960 1290 1550 1680
+pagesize -pg 1 -db -bbox -sgen -180 0 1800 460
+"
+}
+0
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/affhex_pmodssd_v3.vhd b/pb_logique_seq.srcs/sources_1/imports/new/affhex_pmodssd_v3.vhd
new file mode 100644
index 0000000..8e3b048
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/affhex_pmodssd_v3.vhd
@@ -0,0 +1,172 @@
+---------------------------------------------------------------------------------------------

+-- circuit affhex_pmodssd_v3.vhd

+---------------------------------------------------------------------------------------------

+-- Université de Sherbrooke - Département de GEGI

+-- Version         : 3.0

+-- Nomenclature    : 0.8 GRAMS

+-- Date            : revision 16 mai 2019 

+-- Auteur(s)       : Réjean Fontaine, Daniel Dalle

+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)

+--

+-- Outils          : vivado 2016.1 64 bits, vivado 2018.2

+---------------------------------------------------------------------------------------------

+-- Description:

+-- Affichage sur module de 2 chiffes (7 segments) sur PmodSSD 

+-- reference https://reference.digilentinc.com/reference/pmod/pmodssd/start 

+--           PmodSSD™ Reference Manual Doc: 502-126 Digilent, Inc.

+--

+-- Revisions

+-- mise a jour D Dalle 16 mai 2019 controle de la memorisation de l'affichage

+-- mise a jour D Dalle 30 avril 2019 constantes horloges en Hz (pour coherence avec autres modules)

+-- mise a jour D Dalle 17 decembre 2018 constantes horloges en Hz (pour coherence avec autres modules)

+-- mise a jour D Dalle 22 octobre 2018 corrections, simplifications

+-- mise a jour D Dalle 15 octobre documentation affhex_pmodssd_sol_v0.vhd

+-- mise a jour D Dalle 12 septembre pour eviter l'usage d'une horloge interne

+-- mise a jour D Dalle 7 septembre, calcul des constantes.

+-- mise a jour D Dalle 5 septembre 2018, nom affhexPmodSSD, 6 septembre :division horloge

+-- module de commande le l'afficheur 2 segments 2 digits sur pmod

+-- Daniel Dalle revision pour sortir les signaux du connecteur Pmod directement

+-- Daniel Dalle 30 juillet 2018:

+-- revision pour une seule entre sur 8 bits affichee sur les deux chiffres Hexa

+--

+-- Creation selon affhex7segx4v3.vhd 

+-- (Daniel Dalle, Réjean Fontaine Universite de Sherbrooke, Departement GEGI)

+-- 26 septembre 2011, revision 12 juin 2012, 25 janvier 2013, 7 mai 2015

+-- Contrôle de l'afficheur a sept segment (BASYS2 - NEXYS2)

+-- horloge 100MHz et diviseur interne

+---------------------------------------------------------------------------------------------

+-- À faire :

+--

+--

+--

+---------------------------------------------------------------------------------------------

+

+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+use ieee.std_logic_arith.all;

+use ieee.std_logic_unsigned.all;

+

+entity affhexPmodSSD_v3 is

+generic (const_CLK_Hz: integer := 100_000_000);               -- horloge en Hz, typique 100 MHz 

+    Port (   clk        : in   STD_LOGIC;                     -- horloge systeme, typique 100 MHz (preciser par le constante)

+             reset      : in   STD_LOGIC;

+             DA         : in   STD_LOGIC_VECTOR (7 downto 0); -- donnee a afficher sur 8 bits : chiffre hexa position 1 et 0     

+             i_btn      : in   STD_LOGIC_vector(3 downto 0);                     -- demande memorisation affichage continu, si 0: continu

+             JPmod      : out  STD_LOGIC_VECTOR (7 downto 0)  -- sorties directement adaptees au connecteur PmodSSD

+           );

+end affhexPmodSSD_v3;

+

+architecture Behavioral of affhexPmodSSD_v3 is

+

+-- realisation compteur division horloge pour multiplexer affichage SSD

+-- constante pour ajuster selon l horloge pilote du controle des afficheurs

+constant CLK_SSD_Hz_des   : integer  := 5000; --Hz   -- horloge desiree pour raffraichir afficheurs 7 segment

+constant const_div_clk_SSD : integer  := (const_CLK_Hz/CLK_SSD_Hz_des-1);

+constant cdvia  : std_logic_vector (15  downto 0):= conv_std_logic_vector(const_div_clk_SSD, 16); -- donne 5 KHz soit 200 us

+signal   counta : std_logic_vector (15 downto 0) := (others => '0');

+

+signal donn   :  STD_LOGIC_VECTOR (3 downto 0);

+signal DA_sel :  STD_LOGIC_VECTOR (7 downto 0);

+signal segm   :  STD_LOGIC_VECTOR (6 downto 0);

+--

+signal SEL        :  STD_LOGIC;

+signal q_DA       : std_logic_vector (7 downto 0);

+signal q_aff_mem  :  STD_LOGIC;

+

+begin

+

+-- selection chiffre pour affichage

+local_CLK_proc: process(CLK)

+begin

+   if(CLK'event and CLK = '1') then

+      counta <= counta + 1;

+      if (counta = cdvia) then -- devrait se produire aux 200 us approx

+           counta <= (others => '0');

+           SEL <= not SEL;     -- bascule de la selection du chiffre (0 ou 1)

+                               -- SEL devrait avoir periode de 400 us approx          

+      end if;

+   end if;

+end process;

+

+-- multiplexage pour affichage digit

+sel_digit_proc: process(SEL, DA_sel)

+begin

+     if SEL = '0' then 

+            donn <= DA_sel(3 downto 0); 

+        else

+            donn <= DA_sel(7 downto 4);

+        end if;               

+end process;

+

+-- multiplexage pour selection donnee (continue ou bloquée)

+sel_aff_proc: process(i_btn, DA)

+begin

+     if i_btn(2) = '0' then 

+            DA_sel <= DA; 

+        else

+            DA_sel <= q_DA;

+        end if;               

+end process;

+      

+  inst_reg_aff : process ( clk, reset)

+  begin

+     if (reset = '1') then

+        q_DA <= (others => '0');

+     else

+        -- if rising_edge (d_ac_bclk) and d_str_btn(1) = '1' then 

+        if rising_edge (clk) and q_aff_mem = '0' and i_btn(2) ='0' then 

+           q_DA <= DA;

+        end if;

+     end if;

+  end process;

+

+

+fin_continu_process : process (CLK)

+   begin

+      if (rising_edge(CLK)) then

+         q_aff_mem <= i_btn(2);

+      end if;      

+   end process;

+

+-- correspondance des segments des afficheurs

+segment:  process (donn, segm)

+    begin   

+      case donn is

+            --                      "gfedcba"

+            when "0000" => segm  <= "0111111"; -- 0

+            when "0001" => segm  <= "0000110"; -- 1

+            when "0010" => segm  <= "1011011"; -- 2

+            when "0011" => segm  <= "1001111"; -- 3

+            when "0100" => segm  <= "1100110"; -- 4

+            when "0101" => segm  <= "1101101"; -- 5 

+            when "0110" => segm  <= "1111101"; -- 6 

+            when "0111" => segm  <= "0000111"; -- 7 

+            when "1000" => segm  <= "1111111"; -- 8

+            when "1001" => segm  <= "1101111"; -- 9 

+            when "1010" => segm  <= "1110111"; -- A

+            when "1011" => segm  <= "1111100"; -- b 

+            when "1100" => segm  <= "0111001"; -- C 

+            when "1101" => segm  <= "1011110"; -- d 

+            when "1110" => segm  <= "1111001"; -- E

+            when "1111" => segm  <= "1110001"; -- F 

+            when others => segm  <= "0000000";

+       end case;

+    end process;

+

+-- assignation des sorties sur le connecteur Pmod

+sortie_proc: process(segm, SEL)

+begin

+-- contenu segm "gfedcba" pour version Pmod

+   JPmod(0) <= segm(0);

+   JPmod(1) <= segm(1);

+   JPmod(2) <= segm(2);

+   JPmod(3) <= segm(3);

+   JPmod(4) <= segm(4);

+   JPmod(5) <= segm(5);

+   JPmod(6) <= segm(6);

+   JPmod(7) <= SEL;

+end process;

+

+

+end Behavioral;

+

diff --git a/pb_logique_seq.srcs/sources_1/imports/new/attenateur_pwm.vhd b/pb_logique_seq.srcs/sources_1/imports/new/attenateur_pwm.vhd
new file mode 100644
index 0000000..d0c765d
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/attenateur_pwm.vhd
@@ -0,0 +1,71 @@
+---------------------------------------------------------------------------------------------
+-- attenuateur_pwm.vhd 
+---------------------------------------------------------------------------------------------
+-- Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- 
+-- Version        : 1.0
+-- Nomenclature   : ref GRAMS
+-- Date           : 17 sept. 2018
+-- Auteur(s)      : Daniel Dalle
+-- Technologies   : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+-- Outils         : vivado 2018.2 64 bits
+-- 
+--------------------------------
+-- Description
+--------------------------------
+-- Attenuateur par modulation pwm pour sorties leds
+--
+-- 
+---------------------------------------------------------------------------------------------
+-- À FAIRE:
+-- 
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity attenuateur_pwm is
+generic (c_val_seuil: std_logic_vector(7 downto 0)  := "00000111"); 
+    Port ( 
+           CLK        : in STD_LOGIC;      -- Entrée horloge 
+           i_signal    : in  STD_LOGIC;    -- entree 
+           o_signal    : out  STD_LOGIC    -- sortie          
+           );                  
+end attenuateur_pwm;
+
+architecture Behavioral of attenuateur_pwm is
+ 
+ -- constantes pour les diviseurs
+  
+ constant c_seuil         : std_logic_vector(7 downto 0)  := c_val_seuil;
+ signal   d_val_compteur  : std_logic_vector(7 downto 0)  := "00000000";
+ signal   d_signal_on      : std_logic := '1';
+
+
+begin
+                        
+o_signal  <= d_signal_on AND i_signal;
+
+process(CLK)
+begin
+   if(CLK'event and CLK = '1') then
+       d_val_compteur <= d_val_compteur + 1;
+       if (d_val_compteur = "00000000") then  
+            d_signal_on <= '1';                  -- on
+       else if (d_val_compteur = c_seuil) then 
+            d_signal_on <= '0';                  -- off           
+            end if;
+       end if;
+   end if;
+end process;
+
+end Behavioral;
+
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_1.vhd b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_1.vhd
new file mode 100644
index 0000000..3fd0a86
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_1.vhd
@@ -0,0 +1,62 @@
+
+---------------------------------------------------------------------------------------------
+--    calcul_param_1.vhd
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 16 janvier 2020, 4 mai 2020
+--    Auteur(s)       : 
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2019.1 64 bits
+--
+---------------------------------------------------------------------------------------------
+--    Description (sur une carte Zybo)
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+-- À FAIRE: 
+-- Voir le guide de la problématique
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+USE ieee.numeric_std.ALL;
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+----------------------------------------------------------------------------------
+-- 
+----------------------------------------------------------------------------------
+entity calcul_param_1 is
+    Port (
+    i_bclk    : in   std_logic; -- bit clock (I2S)
+    i_reset   : in   std_logic;
+    i_en      : in   std_logic; -- un echantillon present a l'entrée
+    i_ech     : in   std_logic_vector (23 downto 0); -- echantillon en entrée
+    o_param   : out  std_logic_vector (7 downto 0)   -- paramètre calculé
+    );
+end calcul_param_1;
+
+----------------------------------------------------------------------------------
+
+architecture Behavioral of calcul_param_1 is
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+    
+
+---------------------------------------------------------------------------------------------
+--    Description comportementale
+---------------------------------------------------------------------------------------------
+begin 
+
+     o_param <= x"01";    -- temporaire ...
+ 
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_2.vhd b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_2.vhd
new file mode 100644
index 0000000..35574c9
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_2.vhd
@@ -0,0 +1,62 @@
+
+---------------------------------------------------------------------------------------------
+--    calcul_param_2.vhd   (temporaire)
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 16 janvier 2020, 4 mai 2020
+--    Auteur(s)       : 
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2019.1 64 bits
+--
+---------------------------------------------------------------------------------------------
+--    Description (sur une carte Zybo)
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+-- À FAIRE: 
+-- Voir le guide de la problématique
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+USE ieee.numeric_std.ALL;
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+----------------------------------------------------------------------------------
+-- 
+----------------------------------------------------------------------------------
+entity calcul_param_2 is
+    Port (
+    i_bclk    : in   std_logic;   -- bit clock
+    i_reset   : in   std_logic;
+    i_en      : in   std_logic;   -- un echantillon present
+    i_ech     : in   std_logic_vector (23 downto 0);
+    o_param   : out  std_logic_vector (7 downto 0)                                     
+    );
+end calcul_param_2;
+
+----------------------------------------------------------------------------------
+
+architecture Behavioral of calcul_param_2 is
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+    
+
+---------------------------------------------------------------------------------------------
+--    Description comportementale
+---------------------------------------------------------------------------------------------
+begin 
+
+     o_param <= x"02";    -- temporaire ...
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_3.vhd b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_3.vhd
new file mode 100644
index 0000000..4ae1d31
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/calcul_param_3.vhd
@@ -0,0 +1,77 @@
+
+---------------------------------------------------------------------------------------------
+--    calcul_param_3.vhd 
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 6.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 29 janvier 2019, rev 13 février
+--                    : revision 4 mai 2020 élimination de i_lrc
+--    Auteur(s)       : Daniel Dalle
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2018.2 64 bits
+--
+---------------------------------------------------------------------------------------------
+--  Description 
+--  Le troisième paramètre consiste à extraire la valeur pic de l'amplitude
+--  du signal dans une fenêtre glissante couvrant les 48 échantillons les plus récents. 
+---------------------------------------------------------------------------------------------
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+USE ieee.numeric_std.ALL;
+--use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+--use IEEE.std_logic_arith.all;     -- requis pour les constantes telles que cdviv6 etc.
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+----------------------------------------------------------------------------------
+-- **************************************************************************** --
+----------------------------------------------------------------------------------
+entity calcul_param_3 is
+    Port (
+    i_bclk    : in   std_logic;          -- bit clock
+    i_reset   : in   std_logic;          --
+    i_en      : in   std_logic;          -- indique un echantillon present
+ --   i_lrc     : in   std_logic;          -- "Left-Right clock" (I2S)
+    i_ech     : in   std_logic_vector (23 downto 0);  -- valide si en = '1'
+    o_param   : out  std_logic_vector (7 downto 0)    -- valeur paramètre evaluée                               
+    );
+end calcul_param_3;
+
+
+----------------------------------------------------------------------------------
+
+
+architecture Behavioral of calcul_param_3 is
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+    
+
+---------------------------------------------------------------------------------------------
+--    Description comportementale
+---------------------------------------------------------------------------------------------
+begin 
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+-- PAS BESOIN D'IMPLÉMENTER CE PARAMÈTRE
+     o_param <= x"03";    -- temporaire ...
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/circuit_tr_signal.vhd b/pb_logique_seq.srcs/sources_1/imports/new/circuit_tr_signal.vhd
new file mode 100644
index 0000000..6762780
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/circuit_tr_signal.vhd
@@ -0,0 +1,274 @@
+---------------------------------------------------------------------------------------------
+--    circuit_tr_signal.vhd
+---------------------------------------------------------------------------------------------
+--    Circuit de base pour la problématique sur la carte ZYBO avec codec SSM2603
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : rev 10 janvier 2020, 4 mai 2020, 5 janvier 2022
+--    Auteur(s)       : Daniel Dalle, Sébastien Roy, Réjean Fontaine, Julien Rossignol
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1)
+--    Outils          : vivado 2020.2
+--
+---------------------------------------------------------------------------------------------
+--    Description (sur une carte Zybo)
+--    Circuit de fondation pour la problématique, voir la documentation de l'APP et
+--    en particulier l'annexe.
+--
+--    Modification 5 janvier 2022 conversion vers block design
+--    Modification 7 janvier 2020 documentation
+--    Modification 6 mai 2019 introduction de decodeur_i2s_v1b
+--    Developpement initial 2 février 2019
+--
+---------------------------------------------------------------------------------------------
+-- ref documents problématique
+-- ref manual Zybo
+-- https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual
+-- ref schematic (public)
+-- https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf
+-- ref Analog Devices SSM2603 Audio Codec
+-- https://www.analog.com/media/en/technical-documentation/data-sheets/ssm2603.pdf
+--
+-- carte ZYBO Z7-10 (voir les notes de projet)
+-- sur PmodA double cable vers PmodSSD (version preliminaire)
+-- sur PmodB vide      PmodB n'existe pas sur Zybo-Z7-10
+-- sur PmodC ver Pmod8LD
+-- sur PmodD signaux de tests
+-- sur PmodE signaux de tests
+--
+---------------------------------------------------------------------------------------------
+-- À FAIRE:
+-- voir documents problématique
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+----------------------------------------------------------------------------------
+--
+----------------------------------------------------------------------------------
+entity circuit_tr_signal is
+generic ( mode_simulation: std_logic := '0');
+    Port (
+    o_ac_bclk   : out   STD_LOGIC;   -- bit clock ... I2S digital audio clk  ~ mclk /4
+    o_ac_mclk   : out   STD_LOGIC;   -- SSM2603 Master Clock horloge         ~ 12.288 MHz
+    o_ac_muten  : out   STD_LOGIC;   -- DAC Output Mute, Active Low
+    o_ac_pbdat  : out   STD_LOGIC;   -- I²S (Playback Data)
+    o_ac_pblrc  : out   STD_LOGIC;   -- I²S (Playback Channel Clock)         ~ 48. KHz (~ 20.8 us)
+    i_ac_recdat : in    STD_LOGIC;   -- I²S (Record Data)
+    o_ac_reclrc : out   STD_LOGIC;   -- I²S (Record Channel Clock)           ~ 48. KHz (~ 20.8 us)
+    io_ac_scl   : inout STD_LOGIC;   -- horloge I2C SPI
+    io_ac_sda   : inout STD_LOGIC;   -- I2C 2-Wire Control Interface Data Input/Output.
+    --
+    i_btn       : in    std_logic_vector (3 downto 0);
+    i_sw        : in    std_logic_vector (3 downto 0);
+    sysclk      : in    std_logic;
+    o_pmodssd   : out   std_logic_vector (7 downto 0);
+    o_led       : out   std_logic_vector (3 downto 0);
+    o_pmodled   : out   std_logic_vector (7 downto 0);
+    o_led6_r    : out   std_logic;
+    o_led6_g    : out   std_logic
+--
+--    ;                                              -- DIO pour tests avec analyseur logique
+--  DIO      : out   std_logic_vector (15 downto 0)  -- Signaux test pour analyseur logique
+--                                                   -- (connecteurs JD et JE)
+--                                                   -- voir avec fichier contraintes
+    );
+end circuit_tr_signal;
+
+architecture STRUCTURE of circuit_tr_signal is
+
+  constant freq_sys_Hz:  integer := 125_000_000;  -- Hz
+
+  component  init_codec_v2
+    Port (
+         i_reset         : in    std_logic;
+         o_cfg_done      : out   STD_LOGIC;
+         o_cfg_busy      : out   STD_LOGIC;
+         o_ena           : out   STD_LOGIC;  -- pour tests
+       -- pour interface avec partie I2C du codec
+         i_lrc           : in   STD_LOGIC;    -- I²S (Record Channel Clock)           ~ 48. KHz (~ 20.8 us)
+         io_scl          : inout STD_LOGIC;   -- horloge I2C SPI
+         io_sda          : inout STD_LOGIC;   -- I2C 2-Wire Control Interface Data Input/Output.
+            --
+         i_strobe_1000Hz : in    std_logic;
+         clk_p           : in    std_logic
+    );
+  end component;
+
+   component synchro_codec_v1 is
+     generic (cst_CLK_syst_Hz: integer := 100_000_000);  -- valeur par defaut de fréquence de clkm
+     Port (
+       sysclk       : in STD_LOGIC;   -- Entrée  horloge systeme  (typique 125 MHz (1/8 ns) ou 100  ( 1/10 ns))
+       o_clk_0      : out  STD_LOGIC; -- horloge via bufg 50.    MHz  (20 ns)
+       o_mclk       : out  STD_LOGIC; -- horloge via bufg 12.389 MHz  (80,714 ns)
+       o_stb_1000Hz : out  STD_LOGIC; -- strobe durée 1/o_clk_0 sync sur 1000Hz
+       o_stb_1Hz    : out  STD_LOGIC; -- strobe durée 1/o_clk_0 sync sur  1Hz
+       o_S_1Hz      : out  STD_LOGIC; -- Signal temoin 1 Hz
+       o_bclk       : out  STD_LOGIC; -- horloge bit clk (defaut 12.289 MHz / 4 soit 3,07225 MHz  (325.49 ns) )
+       o_reclrc     : out  STD_LOGIC  -- horloge record, play back, sampling rate clock, left right channel (defaut 48 KHz (20,83 us))
+     );
+   end component;
+
+  component attenuateur_pwm
+     generic (c_val_seuil: std_logic_vector(7 downto 0)  := "00001111");
+     port (
+       CLK        : in   STD_LOGIC; -- Entrée horloge
+       i_signal   : in   STD_LOGIC; -- entree
+       o_signal   : out  STD_LOGIC  -- sortie
+     );
+  end component;
+
+  component design_1 is
+  port (
+    i_recdat   : in  STD_LOGIC;
+    i_lrc      : in  STD_LOGIC;
+    i_btn      : in  STD_LOGIC_VECTOR ( 3 downto 0 );
+    i_sw       : in  STD_LOGIC_VECTOR ( 3 downto 0 );
+    clk_100MHz : in  STD_LOGIC;
+    o_pbdat    : out STD_LOGIC_VECTOR ( 0 to 0 );
+    JPmod      : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_param    : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    o_sel_fct  : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    o_sel_par  : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component design_1;
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+
+   signal clk_p           : std_logic;         -- horloge de synchro principale
+   signal d_strobe_1000Hz : std_logic;
+   signal d_strobe_cfg    : std_logic;
+   signal d_strobe_1Hz    : std_logic := '0';
+
+   signal d_T1Hz          : std_logic;
+   signal reset           : std_logic;
+
+   --
+   signal d_sw          :    std_logic_vector (3 downto 0);  -- 4 bits sur Zybo
+   signal d_btn        :    std_logic_vector (3 downto 0);
+   signal d_btn_db        :    std_logic_vector (3 downto 0);
+   -- signal d_str_btn    :    std_logic_vector (3 downto 0);
+
+
+  signal d_ac_bclk   : std_logic;  --out   STD_LOGIC;   -- horloge I2S digital audio  sera mclk/4
+  signal d_ac_mclk   : std_logic;  --out   STD_LOGIC;   -- Master Clock horloge ~ 12.288 MHz
+  signal d_ac_muten  : std_logic;  --out   STD_LOGIC;   -- DAC Output Mute, Active Low
+  signal d_ac_pbdat  : std_logic;  --out   STD_LOGIC;   -- I²S (Playback Data)
+  signal d_ac_pblrc  : std_logic;  --out   STD_LOGIC;   -- I²S (Playback Channel Clock)
+  signal d_ac_recdat : std_logic;  --in    STD_LOGIC;   -- I²S (Record Data)
+  signal d_ac_reclrc : std_logic;  --out   STD_LOGIC;   -- I²S (Record Channel Clock)
+  signal d_ac_scl    : std_logic;  --out   STD_LOGIC;   -- I2C SCLK active ou non
+
+  signal d_cfg_busy : std_logic;
+  signal d_ena      : std_logic;
+  signal d_cfg_done : std_logic;
+
+  signal d_param  : std_logic_vector (7 downto 0);
+  signal d_statut : std_logic_vector (3 downto 0);
+
+---------------------------------------------------------------------------------------------
+--    Description (sur une carte Zybo)
+---------------------------------------------------------------------------------------------
+begin
+
+ inst_synchro : synchro_codec_v1
+  generic map (cst_CLK_syst_Hz => freq_sys_Hz)
+     port map (
+      sysclk       => sysclk,
+      o_clk_0      => clk_p,            -- 50 MHz
+      o_mclk       => d_ac_mclk,        -- 12.288 MHz approx
+      o_stb_1000Hz => d_strobe_1000Hz,
+      o_stb_1Hz    => d_strobe_1Hz,
+      o_S_1Hz      => d_T1Hz,
+      o_bclk       => d_ac_bclk,        -- freq mclk / 4
+      o_reclrc     => d_ac_reclrc
+      );
+
+
+inst_init_codec: init_codec_v2
+--generic ( mode_simulation: std_logic := '0');
+    Port map (
+    i_reset    => reset,
+    o_cfg_done => d_cfg_done,
+    o_cfg_busy => d_cfg_busy,
+    o_ena      => d_ena,
+    --
+    i_lrc      => d_ac_reclrc,
+    io_scl     => io_ac_scl,
+    io_sda     => io_ac_sda,
+    --
+    i_strobe_1000Hz  => d_strobe_cfg,
+    clk_p      => clk_p      -- 50 MHz
+    );
+
+d_strobe_cfg <= d_strobe_1000Hz;
+
+design_1_i: component design_1 port map (
+  JPmod(7 downto 0) => o_pmodssd(7 downto 0),
+  clk_100MHz        => d_ac_bclk,
+  i_btn(3 downto 0) => i_btn(3 downto 0),
+  i_recdat          => d_ac_recdat,
+  i_lrc             => d_ac_reclrc,
+  i_sw(3 downto 0)  => i_sw(3 downto 0),
+  o_pbdat(0)        => d_ac_pbdat,
+  o_param           => d_param,
+  o_sel_fct         => d_statut(3 downto 2),
+  o_sel_par         => d_statut(1 downto 0)
+);
+
+ -- signaux d entree boutons et sw
+    d_btn               <=  i_btn;
+    d_sw                <=  i_sw;
+
+     d_ac_muten <= '1';  -- DAC Output Mute, Active Low (Codec actif) ref SSM2603
+
+     o_led6_r  <=   d_T1Hz;      -- signe de vie sur DEL rouge o_led6_r
+     o_pmodled <=   d_param;
+     o_led     <=   d_statut;
+
+    -- attenuateur pour modérer l'éclat de la led verte o_led6_g
+    inst_att: attenuateur_pwm
+    generic map (c_val_seuil => "00001111")
+    Port map
+      (
+       CLK          => clk_p,
+       i_signal     => d_cfg_done,  -- signal a afficher
+       o_signal     => o_led6_g     -- port led verte
+      );
+
+
+     -- signaux d entree / sortie du codec
+     o_ac_bclk     <=   d_ac_bclk;     --out   STD_LOGIC;   -- horloge I2S digital audio  mclk/4
+     o_ac_mclk     <=   d_ac_mclk;     --out   STD_LOGIC;   -- Master Clock horloge 12.288 MHz  clk_12_288MHz
+     o_ac_muten    <=   d_ac_muten;    --out   STD_LOGIC;   -- DAC Output Mute, Active Low
+     d_ac_recdat   <=   i_ac_recdat;   --in    STD_LOGIC;   -- I²S (Record Data)         provenant du codec
+
+    --signaux vers le codec (avec OBUF)
+    OBUF_o_pblrc : OBUF
+        port map (
+           O => o_ac_pblrc,   -- Buffer output
+           I => d_ac_pblrc    -- Buffer input
+        );
+    OBUF_o_reclrc : OBUF
+        port map (
+           O => o_ac_reclrc,   -- Buffer output
+           I => d_ac_reclrc    -- Buffer input
+        );
+
+    OBUF_o_pbdat : OBUF
+        port map (
+           O => o_ac_pbdat,   -- Buffer output
+           I => d_ac_pbdat    -- Buffer input
+        );
+
+   d_ac_pblrc    <=   d_ac_reclrc;   -- I²S (Record et Playback Channel Clock) communs
+
+end STRUCTURE;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/compteur_nbits.vhd b/pb_logique_seq.srcs/sources_1/imports/new/compteur_nbits.vhd
new file mode 100644
index 0000000..a8cf7d8
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/compteur_nbits.vhd
@@ -0,0 +1,55 @@
+---------------------------------------------------------------------------------------------
+-- circuit compteur_nbits.vhd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 14 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Compteur a avec nombre de bits en parametre generic
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- 
+-- 
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity compteur_nbits is
+generic (nbits : integer := 8);
+   port ( clk             : in    std_logic; 
+          i_en            : in    std_logic; 
+          reset           : in    std_logic; 
+          o_val_cpt       : out   std_logic_vector (nbits-1 downto 0)
+          );
+end compteur_nbits;
+
+architecture BEHAVIORAL of compteur_nbits is               
+-- compteur simple
+
+signal  d_val_cpt: std_logic_vector (nbits-1 downto 0);
+
+BEGIN
+
+compteur_proc : process (clk, reset, i_en)
+   begin
+      if ( reset = '1') then
+          d_val_cpt <= (others =>'0');
+      else
+      if (rising_edge(clk) AND i_en = '1') then
+          d_val_cpt <= d_val_cpt + 1;
+      end if;
+      end if;
+   end process;
+-- sortie
+  o_val_cpt <= d_val_cpt;
+  
+ END Behavioral;
+  
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/conditionne_btn_v7.vhd b/pb_logique_seq.srcs/sources_1/imports/new/conditionne_btn_v7.vhd
new file mode 100644
index 0000000..5ebd314
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/conditionne_btn_v7.vhd
@@ -0,0 +1,120 @@
+---------------------------------------------------------------------------------------------
+-- Circuit conditionne_btn_v7.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 7.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 9 novembre 2018, 27 novembre 2018, 31 janvier 2019, 30 avril 2019, 
+--                   10 janvier 2020
+-- Auteur(s)       : Réjean Fontaine, Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2019.1
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Circuit conditionnement des boutons avec horloge générique
+-- V7 strobe sur transition descendante du bouton (relachement)
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- 
+-- automatiser les calculs de constantes de délai (non requis si frequence 50 MHz pour CLK)
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use     IEEE.std_logic_arith.all;
+use     IEEE.STD_LOGIC_1164.ALL;
+use     IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity conditionne_btn_v7 is
+generic (nbtn : integer := 4;  mode_simul: std_logic := '0');
+port (
+   CLK :    in std_logic;                          -- horloge
+   i_btn :  in std_logic_vector (nbtn-1 downto 0); -- signaux directs des boutons
+   --
+   o_btn_db :  out  std_logic_vector (nbtn-1 downto 0);  -- signaux nettoyés 
+                                                         -- (debounced) des boutons
+   o_strobe_btn : out std_logic_vector (nbtn-1 downto 0) -- impulsion 
+                                                         -- synchrone sur front CLK et transition descendante du bouton (relachement)
+    ); 
+end conditionne_btn_v7;
+
+
+architecture Behavioral of conditionne_btn_v7 is
+
+component strb_gen is
+       Port ( 
+           CLK      : in STD_LOGIC;    -- Entrée  horloge 
+           i_don    : in  STD_LOGIC;   -- signal pour generer strobe au front montant          
+           o_stb    : out  STD_LOGIC   -- strobe synchrone resultant
+           );                           
+   end component;
+ 
+ signal  d_btn: std_logic_vector  (nbtn-1 downto 0);   
+ signal  q0_btn: std_logic_vector (nbtn-1 downto 0);
+ signal  q1_btn: std_logic_vector (nbtn-1 downto 0);  
+ signal  q2_btn: std_logic_vector (nbtn-1 downto 0);   
+     
+ signal ValueCounter  : std_logic_vector(21 downto 0)  := "0000000000000000000000";
+ -- note a 5 MHz, le bit 15 change a une frequende de 76 Hz environ
+ -- note a 50 MHz, le bit 18 change a une frequende de 95 Hz environ
+ -- note a 50 MHz, le bit 16 change a une frequende de 381 Hz environ
+ signal  d_strobe_bit: std_logic;    
+ signal  d_bit_count: std_logic;  
+
+begin
+--  version temporaire ..... 
+--  automatiser les calculs de constantes de délai
+
+process(CLK)
+begin
+   if (CLK'event and CLK = '1') then                -- sur front
+            ValueCounter <= ValueCounter + 1;  
+            d_btn <= i_btn;             
+   end if;
+end process;
+
+
+process (ValueCounter)
+begin
+   if mode_simul = '1' then 
+        d_bit_count <= ValueCounter(2);     -- pour temps simulation: court delai
+    else
+      -- d_bit_count <=  ValueCounter(21);  -- pour temps reel: long delai (trop) 
+       d_bit_count <=  ValueCounter(16);    -- pour temps reel: 
+    end if;
+end process;
+
+
+inst_strb_bit : strb_gen 
+    Port map ( 
+      CLK     =>  CLK,
+      i_don   =>  d_bit_count,
+      o_stb   =>  d_strobe_bit
+      );           
+
+debnc0_process : process (CLK)
+   begin
+      if (rising_edge(CLK)) then
+         q0_btn <= d_btn;
+      end if;      
+   end process;
+
+debnc1_process : process (CLK, d_strobe_bit )
+   begin
+      if ( rising_edge(CLK) and d_strobe_bit = '1') then 
+         q1_btn <= q0_btn;
+      end if;
+   end process;  
+   
+debnc2_process : process (CLK)
+   begin
+      if (rising_edge(CLK)) then
+         q2_btn <= q1_btn;
+      end if;      
+   end process;
+
+o_btn_db     <= q1_btn;
+o_strobe_btn <= not q1_btn AND q2_btn;  -- transition descendante
+--o_strobe_btn <= q1_btn AND not q2_btn;  -- transition montante
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/ctrl_i2c_V4_codec_ssm2603.vhd b/pb_logique_seq.srcs/sources_1/imports/new/ctrl_i2c_V4_codec_ssm2603.vhd
new file mode 100644
index 0000000..690f0ac
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/ctrl_i2c_V4_codec_ssm2603.vhd
@@ -0,0 +1,472 @@
+---------------------------------------------------------------------------------------------
+--    ctrl_i2c_V4_ssm2603.vhd  
+---------------------------------------------------------------------------------------------
+--    controle codec SSM2603 par I2C
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 1.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 20 novembre 2018
+--    Auteur(s)       : Daniel Dalle
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1)
+--    Outils          : vivado 2018.2 64 bits
+--
+--------------------------------
+--    Description
+--------------------------------
+-- Contôle du codec SSM2603 sur une carte Zybo
+--
+--
+-- Note; pour le SSM2603, le bus I2C est controlé de manière telle que
+-- ref page 8 fiche ssm2603.pdf
+--
+-- documents en reference
+-- reference manual Zybo
+-- https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual
+-- schematic (public)
+-- https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf
+-- ref Analog Devices SSM2603 Audio Codec
+-- https://www.analog.com/media/en/technical-documentation/data-sheets/ssm2603.pdf
+-- THE I 2C-BUS SPECIFICATIOn, VERSION 2.1 JANUARY 2000 Philips Semiconductors
+--
+--- revisions
+-- V3: synchronisation, V4 documentation, reset delai
+--------------------------------
+--  À FAIRE:
+-- 
+--------------------------------
+
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- ajoute  par utilisateur...
+
+
+entity ctrl_i2c_V4_ssm2603 is
+-- horloge supposee 50 Mhz
+generic ( c_clk_freq_Hz: integer :=  50_000_000; c_bus_i2c_bps: integer := 100_000);
+
+    Port (
+           clk_master        : in  STD_LOGIC;                     -- horloge maitre pour le controleur (typique 50 MHz)
+           i_reset           : in  STD_LOGIC;
+           i_stb_read        : in  STD_LOGIC;                     -- demarre un cycle de lecture
+           i_stb_write       : in  STD_LOGIC;                     -- demarre un cycle d ecriture
+           i_adr_reg         : in  std_logic_vector(6 downto 0);  -- adresse registres de configuration
+           i_dat_wreg        : in  std_logic_vector(8 downto 0);  -- 9 bits  -- data registre a transmettre
+           o_dat_rreg        : out std_logic_vector(8 downto 0);  -- 9 bits  -- data registre recue
+           io_sda            : inout std_logic ; -- pour developpement
+           io_scl            : inout std_logic ; -- pour developpement
+           o_read_req        : out std_logic ;   -- pour tests 
+           o_write_req       : out std_logic ;   -- pour tests 
+           o_busy            : out std_logic;     -- pour tests;
+           o_ack_error       :   out   STD_LOGIC;  --  -- pour tests;
+           o_ena             :   out   STD_LOGIC;  -- -- pour tests;
+           o_rw              :   out   STD_LOGIC  -- -- pour tests;
+           );
+
+end ctrl_i2c_V4_ssm2603;
+
+architecture Behavioral of ctrl_i2c_V4_ssm2603 is
+
+constant c_master_clk_freq_Hz : integer := c_clk_freq_Hz;
+
+type fsm_codec_ctrl_type is (
+                                 -- read / write sequence SSM2603  *** a developper
+           sta_idle,             --  
+           sta_write_seq_0,      --
+           sta_write_seq_1,      --
+           sta_write_seq_fin,    --
+           --
+           sta_read_seq_0,       --
+           sta_read_seq_1,       --
+           sta_read_seq_2,       --
+           sta_read_seq_3,       --
+           sta_read_seq_4,       --      
+           sta_read_seq_fin      --  
+          );
+        
+        
+constant c_I2C_codec_Addr :  std_logic_vector( 6 downto 0) := "0011010";   -- x"1A"
+
+-- machine etats pour controle i2c_master
+signal fsm_i2c_etat_courant, fsm_i2c_etat_prochain   : fsm_codec_ctrl_type := sta_idle;
+
+signal d_read_req   : std_logic;
+signal d_write_req  : std_logic;
+signal d_reset_req_read_write  : std_logic;
+
+
+-- signaux pour i2c_master,
+signal d_reset_n   : std_logic;
+signal d_ena       : std_logic;
+signal d_codec_adr : std_logic_vector( 6 downto 0) := c_I2C_codec_Addr;
+signal d_rw        : std_logic;
+signal d_data_wr   : std_logic_vector(7 downto 0);
+signal d_data_rd   : std_logic_vector(7 downto 0);
+signal en_d_data1_rd, en_d_data2_rd      : std_logic;
+
+signal d_dat_readreg  : std_logic_vector(8 downto 0);  -- 9 bits
+signal d_busy, q_busy_prec, q_busy      : std_logic;
+
+signal d_delai         :  std_logic_vector(7 downto 0); -- delai en nombre de mclk pour changement etats
+constant c_delai_max   :  std_logic_vector(7 downto 0) := "00101000";   -- 
+signal  d_delai_synch  : std_logic;
+
+signal d_ack_error : std_logic;
+
+
+ 
+component i2c_master
+GENERIC(
+    input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
+    bus_clk   : INTEGER := 400_000);   --speed the i2c bus (scl) will run at in Hz
+  PORT(
+    clk       : IN     STD_LOGIC;                    --system clock
+    reset_n   : IN     STD_LOGIC;                    --active low reset
+    ena       : IN     STD_LOGIC;                    --latch in command
+    addr      : IN     STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+    rw        : IN     STD_LOGIC;                    --'0' is write, '1' is read
+    data_wr   : IN     STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+    busy      : OUT    STD_LOGIC;                    --indicates transaction in progress
+    data_rd   : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+    ack_error : BUFFER STD_LOGIC;                    --flag if improper acknowledge from slave
+    sda       : INOUT  STD_LOGIC;                    --serial data output of i2c bus
+    scl       : INOUT  STD_LOGIC); 
+end component;
+
+BEGIN
+
+inst_i2c_master:  i2c_master 
+ generic map ( input_clk => c_clk_freq_Hz, bus_clk => c_bus_i2c_bps )  
+   port map( 
+      clk        => clk_master,
+      reset_n    => d_reset_n,
+      ena        => d_ena,
+      addr       => d_codec_adr,
+      rw         => d_rw,
+      data_wr    => d_data_wr,
+      busy       => d_busy,
+      data_rd    => d_data_rd,
+      ack_error  => d_ack_error,
+      sda        => io_sda,
+      scl        => io_scl
+   );
+
+
+
+ 
+ -- latch de la requete read ou write 
+  process(clk_master, d_reset_req_read_write, i_reset)
+  begin
+     if (d_reset_req_read_write = '1') or (i_reset = '1') then 
+         d_read_req   <= '0';  -- test
+         d_write_req  <= '0';  -- test
+     else
+     if (clk_master'event and clk_master = '1' and (i_stb_read = '1') )  then
+        d_read_req   <= '1';  -- test
+        end if;     
+     if (clk_master'event and clk_master = '1' and (i_stb_write= '1')  )  then
+        d_write_req  <= '1';  -- test
+     end if; 
+     end if;
+  end process;
+  
+ -- synchro du signal d_busy  au front d'horloge
+  process(clk_master)
+  begin
+     if (clk_master'event and clk_master = '1' )  then
+           q_busy <= d_busy;  
+     end if;
+  end process; 
+  
+  
+  --
+  -- Generation d'un signal d_delai_synch pour assurer duree minimale entre transition...
+  -- NON nécessaire ... utile pour avoir le temps de voir
+  -- des transitions rapides sur l'analyseur logique en periode de mise au point..
+  --
+   compteur_delai : process (clk_master, i_reset)
+     begin
+        if ( i_reset = '1') then
+            d_delai <= (others =>'0');
+            d_delai_synch <= '0';
+        else
+        if (rising_edge(clk_master)) then
+            d_delai <= d_delai + 1;
+            if (d_delai = c_delai_max)  then 
+              d_delai_synch <= '1';
+              d_delai <= (others =>'0');
+              else
+               d_delai_synch <= '0';
+              end if;
+        end if;
+        end if;
+     end process;
+   
+
+-- Assignation du prochain état au front d'horloge
+process(clk_master, i_reset)
+begin
+   if (i_reset= '1') then 
+        fsm_i2c_etat_courant <= sta_idle;
+   else
+    if (clk_master'event and clk_master = '1' and d_delai_synch = '1' )  then
+    --if (clk_master'event and clk_master = '1' )  then
+         fsm_i2c_etat_courant <= fsm_i2c_etat_prochain;
+         q_busy_prec <= q_busy;       
+   end if;
+   end if;
+end process;
+
+
+-- Calcul des transitions du prochain état
+-- nextstate: process(fsm_i2c_etat_courant, d_read_req, d_write_req, q_busy_prec, d_busy)
+nextstate: process(fsm_i2c_etat_courant, d_read_req, d_write_req, q_busy_prec, q_busy)
+begin
+   case fsm_i2c_etat_courant is
+        when sta_idle =>
+             if (d_read_req = '1') and (q_busy = '0')  then
+                   fsm_i2c_etat_prochain   <= sta_read_seq_0;     -- demarrage d'une transaction de lecture
+               --     d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+             else
+               if (d_write_req = '1') and (q_busy = '0')  then
+                   fsm_i2c_etat_prochain   <= sta_write_seq_0;     -- demarrage d'une transaction d'écriture
+               --    d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+                else
+                fsm_i2c_etat_prochain  <= sta_idle; 
+                end if;        
+         end if;
+         --
+         -- Sequence lecture
+         when sta_read_seq_0    => 
+             if (q_busy_prec = '0') and (q_busy = '1') then
+                fsm_i2c_etat_prochain  <= sta_read_seq_1;
+              --  d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+                else
+                fsm_i2c_etat_prochain  <= sta_read_seq_0;
+             end if;
+         when sta_read_seq_1    =>
+             if (q_busy_prec = '0') and (q_busy = '1')then
+               fsm_i2c_etat_prochain  <= sta_read_seq_2;
+              -- d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+               else
+               fsm_i2c_etat_prochain  <= sta_read_seq_1;
+             end if;                  
+         when sta_read_seq_2    => 
+             if (q_busy = '0') then
+               fsm_i2c_etat_prochain  <= sta_read_seq_fin;
+              -- d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+               else
+               fsm_i2c_etat_prochain  <= sta_read_seq_2;
+             end if;
+         when sta_read_seq_fin  =>
+              fsm_i2c_etat_prochain  <= sta_idle;
+               -- d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+         --
+         -- Sequence ecriture
+         when sta_write_seq_0    => 
+              if (q_busy_prec = '0') and (q_busy = '1') then
+                fsm_i2c_etat_prochain  <= sta_write_seq_1;
+              -- d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+              else
+                fsm_i2c_etat_prochain  <= sta_write_seq_0;
+              end if;
+         when sta_write_seq_1    => 
+               if (q_busy_prec = '0') and (q_busy = '1') then
+                 fsm_i2c_etat_prochain  <= sta_write_seq_fin; 
+               --d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+               else
+                 fsm_i2c_etat_prochain  <= sta_write_seq_1;              
+              end if;     
+
+         when sta_write_seq_fin    => 
+              fsm_i2c_etat_prochain  <= sta_idle;
+              --d_ack_debug  <= not d_ack_debug;    -- debug temporaire...
+              
+         when others =>
+             fsm_i2c_etat_prochain <= sta_idle;
+   end case;
+end process;
+
+-- calcul des sorties de la MEF de controle
+sorties: process(fsm_i2c_etat_courant, i_adr_reg, i_dat_wreg, d_data_rd)
+-- Calcul des sorties
+begin
+--
+-- documentation ****************************************************
+--   Sequence non déterminée
+--        sta idle
+--                   sorties:
+--                        q_busy est 0
+--                        pas d'opération
+--                   transitions
+--                        strobe i_stb_read détecté, prochain etat est sta_read_seq_0  sans autre condition
+--                        strobe i_stb_write détecté, prochain etat est sta_write_seq_0  sans autre condition
+--                        d_rw  <= '1' ; --  commande prochaine requise est lecture (premiere partie contenu registre)
+--                   transitions prochaine
+--                        q_busy  passe de 0 a 1 : la commande a ete saisie par codec, prochain etat sta_read_seq2
+--        sta_read_seq2
+--                        d_rw  <= '1' ; --  commande requise est lecture (seconde partie contenu registre)
+--                   transitions prochaine
+--                        quand q_busy = '0' la lecture premiere partie est disponible
+--                        q_busy  passe de 0 a 1 : la commande a ete saisie par codec, prochain etat sta_read_seq_fin
+---
+--        sta_read_seq_fin
+--                        le resultat de lecture est disponible  (seconde partie contenu registre)
+--                   transitions
+--                        prochain etat sta_idle sans condition
+--
+--   Sequence ecriture
+--        sta_read_seq_fin
+--                    d_ena <= '0';   -- pas de prochaine commande
+--                        le resultat de lecture est disponible  (seconde partie contenu registre)
+--                   transitions
+--                        prochain etat sta_idle sans condition
+--
+--   Sequence ecriture
+--        sta_write_seq0
+--                        d_ena <= '1';  -- initialiser transaction  (inferred latch)
+--                        d_rw  <= '0' ; -- commande requise est ecriture
+--                        donnée a écrire sur d_data_wr (numero registre codec)  + 1 bit du contenu du registre
+--                        adresse I2C déja en place sur addr
+--                   transitions
+--                        q_busy  passe de 0 a 1 : la commande est saisie par codec, prochain etat sta_write_seq0
+--        sta_write_se1
+--                        d_rw  <= '0' ; --  commande requise est ecriture (seconde partie contenu registre 8 bits )
+--                                       --  donnée a écrire sur d_data_wr (seconde partie contenu registre 8 bits )
+--                   transitions
+--                        q_busy  passe de 0 a 1 : la commande a ete saisie par codec, prochain etat sta_write_seq_fin
+--        sta_write_seq_fin
+--                        le resultat de lecture est disponible  (seconde partie contenu registre)
+--                   transitions
+--                        prochain etat sta_idle sans condition
+--
+
+   case fsm_i2c_etat_courant is
+       when sta_idle           =>
+           d_ena       <= '0';
+           --
+           d_reset_req_read_write <='0'; 
+           d_rw  <= '1';  -- par defaut
+           d_data_wr(7 downto 0 ) <= (others => '0');
+           en_d_data1_rd  <= '0';  
+           en_d_data2_rd  <= '0';         
+       -- Sequence lecture 
+       when sta_read_seq_0   =>   -- on arrive ici avec q_busy = '0'
+        -- l'adresse I2C est deja fixee tours la meme dans ce contexte d_codec_adr
+          d_ena <= '1'; 
+          d_rw  <= '0';        -- commande ecriture (pour adresse registre codec)
+          d_data_wr(7 downto 0 ) <= i_adr_reg (6 downto 0) & '0';  --   data tx : adresse registre codec  & '0'          
+          d_reset_req_read_write <='0';
+          --
+          d_reset_req_read_write <='0'; 
+          en_d_data1_rd  <= '0';  
+          en_d_data2_rd  <= '0';
+          
+       when sta_read_seq_1   =>  -- le codec a repondu en levant q_busy = '1'
+          d_ena <= '1';  
+          d_rw  <= '1';        --  (pour lire premiere partie contenu registre)
+          d_reset_req_read_write <='1';
+          --
+          d_data_wr(7 downto 0 ) <= (others => '0');
+          en_d_data1_rd  <= '0';  
+          en_d_data2_rd  <= '0';
+                       
+       when sta_read_seq_2   =>   -- enregiste les 8 bits lu et enchaine une nouvelle commande immediatement  lire 1 bits (parmi 8)
+                                  -- q_busy passse a zero -> transition vers le suivant
+          d_ena <= '1'; 
+          d_rw  <= '1';           --  (pour lire seconde partie contenu registre)
+          en_d_data1_rd  <= '1';  -- 
+          d_reset_req_read_write <='0';
+          --
+          d_data_wr(7 downto 0 ) <= (others => '0'); 
+          en_d_data2_rd  <= '0';        
+          
+        when sta_read_seq_fin   => 
+          d_ena <= '0';
+          en_d_data2_rd  <= '1';   --
+          d_reset_req_read_write <='0'; 
+          d_rw  <= '1';
+          d_data_wr(7 downto 0 ) <= (others => '0');
+          en_d_data1_rd  <= '0';  
+          --  
+          --
+          --
+          --
+       when sta_write_seq_0    => 
+           -- l'adresse I2C est deja fixee tours la meme dans ce contexte d_codec_adr
+           d_ena <= '1';         --
+           d_rw  <= '0';         --
+           d_data_wr(7 downto 0 ) <= i_adr_reg (6 downto 0) & i_dat_wreg(8);  --  data tx : adresse registre codec & 1 bit data
+           --
+           d_reset_req_read_write <='0'; 
+           en_d_data1_rd  <= '0';  
+           en_d_data2_rd  <= '0';              
+      -- 
+       when sta_write_seq_1    => 
+           d_ena <= '1';  
+           d_rw  <= '0'; 
+           d_data_wr(7 downto 0 ) <= i_dat_wreg (7 downto 0);                 --  data tx :  8 bits data    
+           d_reset_req_read_write <='1';
+           --
+           en_d_data1_rd  <= '0';  
+           en_d_data2_rd  <= '0';    
+       --    
+       when sta_write_seq_fin    => 
+           d_ena <= '0';   
+           d_reset_req_read_write <='0';           
+           --
+           d_rw  <= '1';
+           d_data_wr(7 downto 0 ) <= (others => '0');
+           en_d_data1_rd  <= '0';  
+           en_d_data2_rd  <= '0';        
+       --when others         => NULL;
+       when others    => 
+            d_ena       <= '0';
+            d_reset_req_read_write <='0'; 
+            d_rw  <= '1';
+            d_data_wr(7 downto 0 ) <= (others => '0');
+            en_d_data1_rd  <= '0';  
+            en_d_data2_rd  <= '0'; 
+ end case;
+
+ end process;
+ 
+ 
+inst_dat_read:  process(clk_master, i_reset)
+ begin
+    if (i_reset= '1') then 
+         d_dat_readreg(8 downto 0) <= (others => '0');
+    else
+        if (clk_master'event and clk_master = '1') then
+            if   (en_d_data1_rd = '1')  then
+               d_dat_readreg(7 downto 0)  <= d_data_rd ; 
+               else if (en_d_data2_rd = '1') then 
+                d_dat_readreg(8)  <= d_data_rd(0);  
+               end if;
+            end if;    
+        end if;
+     end if;
+ end process;
+
+
+ --
+  d_reset_n <= not i_reset;
+  o_busy <=  q_busy;
+  o_ack_error   <=  d_ack_error;
+  o_ena         <=  d_ena;
+  o_rw          <=  d_rw;
+              
+  o_read_req    <= d_read_req;
+  o_write_req   <= d_write_req;
+  o_dat_rreg    <= d_dat_readreg;
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/gen_clk_codec.vhd b/pb_logique_seq.srcs/sources_1/imports/new/gen_clk_codec.vhd
new file mode 100644
index 0000000..09ca6e9
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/gen_clk_codec.vhd
@@ -0,0 +1,123 @@
+---------------------------------------------------------------------------------------------
+--	gen_clk_codec.vhd
+---------------------------------------------------------------------------------------------
+--	Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+--	Université de Sherbrooke - Département de GEGI
+--	
+--	Version 		: 1.0
+--	Nomenclature	: ref GRAMS
+--	Date			: 30 octobre 2018, ..., 24 janvier 2019, 25 janvier
+--	Auteur(s)		: Daniel Dalle
+--  Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1)
+--  Outils          : vivado 2018.2 64 bits
+--	
+--------------------------------
+--	Description
+--------------------------------
+-- Génération de signaux de synchronisation, incluant des "strobes"
+-- (utilise un PLL)
+-- Ref:
+-- 7 Series Libraries Guide www.xilinx.com 418 UG953 (v2016.3) October 5, 2016
+--   (pages 425 PLLE2_BASE)
+--
+-- revisions
+-- mise a jour   D Dalle 24 janvier 2019   commentaires
+-- mise a jour   D Dalle 18 janvier 2019   synchronisation o_reclrc
+-- mise a jour   D Dalle  9 janvier 2019   bufg sur o_bclk 
+-- Développement D Dalle 30 octobre 2018, 7 novembre 2018, 4 janvier 2019
+---------------------------------------------------------------------------------------------
+--	À FAIRE:
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity gen_clk_codec is
+port  (
+   i_rst    : in STD_LOGIC;   -- entree reset
+   m_clk    : in STD_LOGIC;   -- Entrée horloge maitre codec  12.389 MHz
+   o_bclk   : out  STD_LOGIC; -- horloge bit clk:  freq m_clk MHz / 4 soit 3,097 MHz 
+   o_reclrc : out  STD_LOGIC  -- horloge record, play back, sampling rate clock, left right channel 48,021 KHz 
+  );
+end gen_clk_codec;
+
+architecture Behavioral of gen_clk_codec is
+
+    signal d_bclk       : std_logic := '0';   -- horloge I2S digital audio (50 MHz pour cet exemple)
+    signal d_reclrc     : std_logic := '0';   -- I²S (Record Channel Clock)  
+    signal q_reclrc     : std_logic;          -- I²S (Record Channel Clock)  synchronisation
+    signal d_cpt_reclrc : std_logic_vector (7 downto 0) := "00000000";  
+    signal d_cpt_bclk   : std_logic_vector (1 downto 0) := "00"; 
+    
+    
+    begin
+
+-- generateur horloge echantillonnage (ADC sampling Rate) et transfert binaire 
+------------------------------------------------------------------------
+-- ref SSM2603 data sheet page 25 (defaut pour MCLK = 12.288 MHz)
+-- RECLRC : MCLK / 256   BCLK : RECLRC / 4
+
+reclrc_proc: process(m_clk)
+       begin
+           if rising_edge(m_clk) then
+              if i_rst = '1' then
+                 d_reclrc <= '0';
+                 d_cpt_reclrc  <= "00000000"; 
+              else
+                 if d_cpt_reclrc = 128 then -- 256/2
+                    d_cpt_reclrc <= "00000000"; 
+                    d_reclrc <= not d_reclrc;
+                 else
+                    d_cpt_reclrc <= d_cpt_reclrc + 1;
+                 end if;
+              end if;
+           end if;
+        end process reclrc_proc;
+  
+bclk_proc: process(m_clk)    
+       begin
+           if rising_edge(m_clk) then
+              if i_rst = '1' then
+                 d_bclk <= '0';
+                 d_cpt_bclk <= "00"; 
+              else
+                 if d_cpt_bclk = 01 then
+                    d_cpt_bclk <= "00"; 
+                    d_bclk <= not d_bclk;
+                 else
+                    d_cpt_bclk <= d_cpt_bclk + 1;
+                 end if;
+              end if;
+           end if;
+        end process bclk_proc;
+  
+--  lrc_proc: process(m_clk)    
+--    begin
+--       if falling_edge(m_clk) then
+--              q_reclrc <= d_reclrc;  
+--          end if;
+--       end process lrc_proc;
+ 
+ -- forme 25 janvier
+  lrc_proc: process(d_bclk)    
+    begin
+       if falling_edge(d_bclk) then
+              q_reclrc <= d_reclrc;  
+          end if;
+       end process lrc_proc; 
+ 
+ 
+  o_reclrc <= q_reclrc;    
+  
+  -- o_bclk <= d_bclk;  
+  ClockBufer1: bufg           -- revision 9 janvier 2018
+      port map(
+          I    => d_bclk,
+          O    => o_bclk
+          );
+        
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/i2c_master.vhd b/pb_logique_seq.srcs/sources_1/imports/new/i2c_master.vhd
new file mode 100644
index 0000000..a4fe165
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/i2c_master.vhd
@@ -0,0 +1,247 @@
+--------------------------------------------------------------------------------

+--

+--   FileName:         i2c_master.vhd

+--   Dependencies:     none

+--   Design Software:  Quartus II 64-bit Version 13.1 Build 162 SJ Full Version

+--

+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY

+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT

+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY

+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL

+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF

+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS

+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),

+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.

+--

+--   Version History

+--   Version 1.0 11/01/2012 Scott Larson

+--     Initial Public Release

+--   Version 2.0 06/20/2014 Scott Larson

+--     Added ability to interface with different slaves in the same transaction

+--     Corrected ack_error bug where ack_error went 'Z' instead of '1' on error

+--     Corrected timing of when ack_error signal clears

+--   Version 2.1 10/21/2014 Scott Larson

+--     Replaced gated clock with clock enable

+--     Adjusted timing of SCL during start and stop conditions

+--   Version 2.2 02/05/2015 Scott Larson

+--     Corrected small SDA glitch introduced in version 2.1

+-- 

+--------------------------------------------------------------------------------

+

+LIBRARY ieee;

+USE ieee.std_logic_1164.all;

+USE ieee.std_logic_unsigned.all;

+

+ENTITY i2c_master IS

+  GENERIC(

+    input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz

+    bus_clk   : INTEGER := 400_000);   --speed the i2c bus (scl) will run at in Hz

+  PORT(

+    clk       : IN     STD_LOGIC;                    --system clock

+    reset_n   : IN     STD_LOGIC;                    --active low reset

+    ena       : IN     STD_LOGIC;                    --latch in command

+    addr      : IN     STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave

+    rw        : IN     STD_LOGIC;                    --'0' is write, '1' is read

+    data_wr   : IN     STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave

+    busy      : OUT    STD_LOGIC;                    --indicates transaction in progress

+    data_rd   : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave

+    ack_error : BUFFER STD_LOGIC;                    --flag if improper acknowledge from slave

+    sda       : INOUT  STD_LOGIC;                    --serial data output of i2c bus

+    scl       : INOUT  STD_LOGIC);                   --serial clock output of i2c bus

+END i2c_master;

+

+ARCHITECTURE logic OF i2c_master IS

+  CONSTANT divider  :  INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl

+  TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states

+  SIGNAL state         : machine;                        --state machine

+  SIGNAL data_clk      : STD_LOGIC;                      --data clock for sda

+  SIGNAL data_clk_prev : STD_LOGIC;                      --data clock during previous system clock

+  SIGNAL scl_clk       : STD_LOGIC;                      --constantly running internal scl

+  SIGNAL scl_ena       : STD_LOGIC := '0';               --enables internal scl to output

+  SIGNAL sda_int       : STD_LOGIC := '1';               --internal sda

+  SIGNAL sda_ena_n     : STD_LOGIC;                      --enables internal sda to output

+  SIGNAL addr_rw       : STD_LOGIC_VECTOR(7 DOWNTO 0);   --latched in address and read/write

+  SIGNAL data_tx       : STD_LOGIC_VECTOR(7 DOWNTO 0);   --latched in data to write to slave

+  SIGNAL data_rx       : STD_LOGIC_VECTOR(7 DOWNTO 0);   --data received from slave

+  SIGNAL bit_cnt       : INTEGER RANGE 0 TO 7 := 7;      --tracks bit number in transaction

+  SIGNAL stretch       : STD_LOGIC := '0';               --identifies if slave is stretching scl

+BEGIN

+

+  --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)

+  PROCESS(clk, reset_n)

+    VARIABLE count  :  INTEGER RANGE 0 TO divider*4;  --timing for clock generation

+  BEGIN

+    IF(reset_n = '0') THEN                --reset asserted

+      stretch <= '0';

+      count := 0;

+    ELSIF(clk'EVENT AND clk = '1') THEN

+      data_clk_prev <= data_clk;          --store previous value of data clock

+      IF(count = divider*4-1) THEN        --end of timing cycle

+        count := 0;                       --reset timer

+      ELSIF(stretch = '0') THEN           --clock stretching from slave not detected

+        count := count + 1;               --continue clock generation timing

+      END IF;

+      CASE count IS

+        WHEN 0 TO divider-1 =>            --first 1/4 cycle of clocking

+          scl_clk <= '0';

+          data_clk <= '0';

+        WHEN divider TO divider*2-1 =>    --second 1/4 cycle of clocking

+          scl_clk <= '0';

+          data_clk <= '1';

+        WHEN divider*2 TO divider*3-1 =>  --third 1/4 cycle of clocking

+          scl_clk <= '1';                 --release scl

+          IF(scl = '0') THEN              --detect if slave is stretching clock

+            stretch <= '1';

+          ELSE

+            stretch <= '0';

+          END IF;

+          data_clk <= '1';

+        WHEN OTHERS =>                    --last 1/4 cycle of clocking

+          scl_clk <= '1';

+          data_clk <= '0';

+      END CASE;

+    END IF;

+  END PROCESS;

+

+  --state machine and writing to sda during scl low (data_clk rising edge)

+  PROCESS(clk, reset_n)

+  BEGIN

+    IF(reset_n = '0') THEN                 --reset asserted

+      state <= ready;                      --return to initial state

+      busy <= '1';                         --indicate not available

+      scl_ena <= '0';                      --sets scl high impedance

+      sda_int <= '1';                      --sets sda high impedance

+      ack_error <= '0';                    --clear acknowledge error flag

+      bit_cnt <= 7;                        --restarts data bit counter

+      data_rd <= "00000000";               --clear data read port

+    ELSIF(clk'EVENT AND clk = '1') THEN

+      IF(data_clk = '1' AND data_clk_prev = '0') THEN  --data clock rising edge

+        CASE state IS

+          WHEN ready =>                      --idle state

+            IF(ena = '1') THEN               --transaction requested

+              busy <= '1';                   --flag busy

+              addr_rw <= addr & rw;          --collect requested slave address and command

+              data_tx <= data_wr;            --collect requested data to write

+              state <= start;                --go to start bit

+            ELSE                             --remain idle

+              busy <= '0';                   --unflag busy

+              state <= ready;                --remain idle

+            END IF;

+          WHEN start =>                      --start bit of transaction

+            busy <= '1';                     --resume busy if continuous mode

+            sda_int <= addr_rw(bit_cnt);     --set first address bit to bus

+            state <= command;                --go to command

+          WHEN command =>                    --address and command byte of transaction

+            IF(bit_cnt = 0) THEN             --command transmit finished

+              sda_int <= '1';                --release sda for slave acknowledge

+              bit_cnt <= 7;                  --reset bit counter for "byte" states

+              state <= slv_ack1;             --go to slave acknowledge (command)

+            ELSE                             --next clock cycle of command state

+              bit_cnt <= bit_cnt - 1;        --keep track of transaction bits

+              sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus

+              state <= command;              --continue with command

+            END IF;

+          WHEN slv_ack1 =>                   --slave acknowledge bit (command)

+            IF(addr_rw(0) = '0') THEN        --write command

+              sda_int <= data_tx(bit_cnt);   --write first bit of data

+              state <= wr;                   --go to write byte

+            ELSE                             --read command

+              sda_int <= '1';                --release sda from incoming data

+              state <= rd;                   --go to read byte

+            END IF;

+          WHEN wr =>                         --write byte of transaction

+            busy <= '1';                     --resume busy if continuous mode

+            IF(bit_cnt = 0) THEN             --write byte transmit finished

+              sda_int <= '1';                --release sda for slave acknowledge

+              bit_cnt <= 7;                  --reset bit counter for "byte" states

+              state <= slv_ack2;             --go to slave acknowledge (write)

+            ELSE                             --next clock cycle of write state

+              bit_cnt <= bit_cnt - 1;        --keep track of transaction bits

+              sda_int <= data_tx(bit_cnt-1); --write next bit to bus

+              state <= wr;                   --continue writing

+            END IF;

+          WHEN rd =>                         --read byte of transaction

+            busy <= '1';                     --resume busy if continuous mode

+            IF(bit_cnt = 0) THEN             --read byte receive finished

+              IF(ena = '1' AND addr_rw = addr & rw) THEN  --continuing with another read at same address

+                sda_int <= '0';              --acknowledge the byte has been received

+              ELSE                           --stopping or continuing with a write

+                sda_int <= '1';              --send a no-acknowledge (before stop or repeated start)

+              END IF;

+              bit_cnt <= 7;                  --reset bit counter for "byte" states

+              data_rd <= data_rx;            --output received data

+              state <= mstr_ack;             --go to master acknowledge

+            ELSE                             --next clock cycle of read state

+              bit_cnt <= bit_cnt - 1;        --keep track of transaction bits

+              state <= rd;                   --continue reading

+            END IF;

+          WHEN slv_ack2 =>                   --slave acknowledge bit (write)

+            IF(ena = '1') THEN               --continue transaction

+              busy <= '0';                   --continue is accepted

+              addr_rw <= addr & rw;          --collect requested slave address and command

+              data_tx <= data_wr;            --collect requested data to write

+              IF(addr_rw = addr & rw) THEN   --continue transaction with another write

+                sda_int <= data_wr(bit_cnt); --write first bit of data

+                state <= wr;                 --go to write byte

+              ELSE                           --continue transaction with a read or new slave

+                state <= start;              --go to repeated start

+              END IF;

+            ELSE                             --complete transaction

+              state <= stop;                 --go to stop bit

+            END IF;

+          WHEN mstr_ack =>                   --master acknowledge bit after a read

+            IF(ena = '1') THEN               --continue transaction

+              busy <= '0';                   --continue is accepted and data received is available on bus

+              addr_rw <= addr & rw;          --collect requested slave address and command

+              data_tx <= data_wr;            --collect requested data to write

+              IF(addr_rw = addr & rw) THEN   --continue transaction with another read

+                sda_int <= '1';              --release sda from incoming data

+                state <= rd;                 --go to read byte

+              ELSE                           --continue transaction with a write or new slave

+                state <= start;              --repeated start

+              END IF;    

+            ELSE                             --complete transaction

+              state <= stop;                 --go to stop bit

+            END IF;

+          WHEN stop =>                       --stop bit of transaction

+            busy <= '0';                     --unflag busy

+            state <= ready;                  --go to idle state

+        END CASE;    

+      ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN  --data clock falling edge

+        CASE state IS

+          WHEN start =>                  

+            IF(scl_ena = '0') THEN                  --starting new transaction

+              scl_ena <= '1';                       --enable scl output

+              ack_error <= '0';                     --reset acknowledge error output

+            END IF;

+          WHEN slv_ack1 =>                          --receiving slave acknowledge (command)

+            IF(sda /= '0' OR ack_error = '1') THEN  --no-acknowledge or previous no-acknowledge

+              ack_error <= '1';                     --set error output if no-acknowledge

+            END IF;

+          WHEN rd =>                                --receiving slave data

+            data_rx(bit_cnt) <= sda;                --receive current slave data bit

+          WHEN slv_ack2 =>                          --receiving slave acknowledge (write)

+            IF(sda /= '0' OR ack_error = '1') THEN  --no-acknowledge or previous no-acknowledge

+              ack_error <= '1';                     --set error output if no-acknowledge

+            END IF;

+          WHEN stop =>

+            scl_ena <= '0';                         --disable scl

+          WHEN OTHERS =>

+            NULL;

+        END CASE;

+      END IF;

+    END IF;

+  END PROCESS;  

+

+  --set sda output

+  WITH state SELECT

+    sda_ena_n <= data_clk_prev WHEN start,     --generate start condition

+                 NOT data_clk_prev WHEN stop,  --generate stop condition

+                 sda_int WHEN OTHERS;          --set to internal sda signal    

+      

+  --set scl and sda outputs

+  scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';

+  sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';

+  

+END logic;

diff --git a/pb_logique_seq.srcs/sources_1/imports/new/init_codec_v2.vhd b/pb_logique_seq.srcs/sources_1/imports/new/init_codec_v2.vhd
new file mode 100644
index 0000000..a17a0cc
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/init_codec_v2.vhd
@@ -0,0 +1,336 @@
+
+---------------------------------------------------------------------------------------------
+--    init_codec_v2.vhd  
+---------------------------------------------------------------------------------------------
+--    configuration conversion A/N  par codec SSM2603 sur la carte ZYBO
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 13 janvier 2018, révision 21 janvier 2019, 1 février 2019, 20 février (delai ajusté)
+--    Auteur(s)       : Daniel Dalle
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2018.2 64 bits
+--
+---------------------------------------------------------------------------------------------
+--    Description (sur une carte Zybo)
+-- initialisation du Codec SSM2603 de la carte Zybo-z7-10 (ou 20)
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+--
+-- ref manual Zybo
+-- https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual
+-- ref schematic (public)
+-- https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf
+-- ref Analog Devices SSM2603 Audio Codec
+-- https://www.analog.com/media/en/technical-documentation/data-sheets/ssm2603.pdf
+--
+--------------------------------
+--    À FAIRE:
+-- Espacement de 4 ms entre chaque trame I2C (pour respecter délai power-on et activation) ref. SSM2603.pdf
+-- Restructurer pour définir un module d'initialisation du codec qui peut être sous-module
+-- dans la hiérarchie et utilisé comme boite noire.
+-- verifier R4 Analog audio path (LINE ou MIC)  OK, mais a suivre 11 janvier 2019
+-- En particlier, pour la suite, donner une option de configuration MIC ou LINE (actuellement choix fixe)
+--------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+USE ieee.numeric_std.ALL;
+--use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+--use IEEE.std_logic_arith.all;     -- requi pour les constantes telles que cdviv6 etc.
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- *****************************************************************************--
+----------------------------------------------------------------------------------
+entity init_codec_v2 is
+--generic ( mode_simulation: std_logic := '0');  -- developpement futur si requis
+    Port (   
+      -- mode de controle necessaire ???   
+    i_reset      : in    std_logic;
+    o_cfg_done   : out   STD_LOGIC; 
+    o_cfg_busy   : out   STD_LOGIC; 
+    o_ena        : out   STD_LOGIC;  -- pour tests
+    --
+    -- Signaux I2C
+    i_lrc           :   in   STD_LOGIC;    -- I²S (Record Channel Clock) 
+    io_scl          :   inout STD_LOGIC;   -- horloge I2C SPI
+    io_sda          :   inout STD_LOGIC;   -- I2C 2-Wire Control Interface Data Input/Output.
+    --
+    i_strobe_1000Hz : in    std_logic;     -- pour synchro de configuration
+    clk_p      : in    std_logic
+    );
+end init_codec_v2;
+
+
+----------------------------------------------------------------------------------
+
+architecture Behavioral of init_codec_v2 is
+   
+   constant nbreboutons:  integer := 4;
+   constant freq_sys_Hz:  integer := 125_000_000;  -- Hz
+
+type register_cfg is array (0 to 31) of std_logic_vector (15 downto 0);
+ --configuration programmee du codec (dans un ordre determine ref audio.c )
+signal cfg_ssm2603 : register_cfg := (
+-- adresse reg    contenu             seq registre
+-- 15     9        8        0
+"0001111"     & "000000000", --    0    R15 Software reset
+"0000110"     & "000110000", --    1    R6 Power management
+                                     -- R6 D8=0;
+                                     -- R6 D7=0; pwroff         : power up;
+                                     -- R6 D6=0; clkout power   : power up;
+                                     -- R6 D5=1; crystal power  : power down;
+                                     -- R6 D4=1; output power   : power down;
+                                     -- R6 D3=0; DAC power      : power up;
+                                     -- R6 D2=0; ADC power      : power up;
+                                     -- R6 D1=0; MIC in power   : power up;
+                                     -- R6 D0=0; LINE in power  : power up;
+                                      
+"0000000"     & "000010111", --    2    R0 Left-channel ADC input volume
+                                      --   R0: disable loading left to right;  disable mute; 0 dB
+"0000001"     & "000010111", --    3    R1 Right-channel ADC input volume
+                                      --    R1: disable loading right to left;  disable mute; 0 dB
+                                   
+"0000010"     & "001111001", --    4    R2 Left-channel DAC volume  (defaut / datasheet)
+                                               --   R2 disable left ch head phone vol data to right; volume 0dB (defaut / datasheet)
+"0000011"     & "001111001", --    5    R3 Right-channel DAC volume  (defaut / datasheet)
+                                              --    R3 disable right ch head phone vol data to left; volume 0dB (defaut / datasheet)                                   
+--"0000010"     & "001101001", --    4    R2 Left-channel DAC volume  (defaut / datasheet)
+--                                         --   R2 disable left ch head phone vol data to right; volume -16 dB (conseillé avec écouteurs....)
+--"0000011"     & "001101001", --    5    R3 Right-channel DAC volume  (defaut / datasheet)
+--                                        --    R3 disable right ch head phone vol data to left; volume -16 dB  (conseillé avec écouteurs....)                                           
+                         
+--          "0000100"     & "000000100", --    6    R4 Analog audio path    -- audio.c  INSEL = mic
+"0000100"     & "000010000", --    6    R4 Analog audio path    --          INSEL = LINE   
+                              -- R4 D8=0;                          : 0        (def)
+                              -- R4 D7=0; |                        : 0
+                              -- R4 D6=0; | mic sidetone gain ctrl : 00 -6dB   (def)
+                              -- R4 D5=0; sidetone_en              : 0 disable (def)
+                              -- R4 D4=1; DACSEL  (mix DAC output) : 1 select DAC
+                              -- R4 D3=0; BypAss                   : 0 = Bypass disabled
+                              -- R4 D2=0; INSEL                    : 0 = LINE input select to ADC (def)  ***** 1: MIC
+                              -- R4 D1=0; MUTEMIC                  : 0 (disabled)  
+                              -- R4 D0=0; MICBOOST                 : 0 = 0 dB (def);          
+"0000101"     & "000000000", --    7    R5 Digital audio path
+"0000111"     & "000000010", --    8    R7 Digital audio I/F
+                           --                   ref data sheet page 25/31
+                           --                   24 bits I2S mode, sampling ADC 48 KHz   DAC 48 KHz
+"0001000"     & "000000000", --    9    R8 Sampling rate
+"0001001"     & "000000001", --   10    R9 Active
+"0000110"     & "000100000", --   11    R6 Power management
+                               -- R6 D8=0;
+                               -- R6 D7=0; pwroff         : power up;
+                               -- R6 D6=0; clkout power   : power up;
+                               -- R6 D5=1; crystal power  : power down;
+                               -- R6 D4=0; output power   : power up;
+                               -- R6 D3=0; DAC power      : power up;
+                               -- R6 D2=0; ADC power      : power up;
+                               -- R6 D1=0; MIC in power   : power up;
+others =>
+"1111111"     & "000000000"  --   code adresse de registre non reelle signifie extremite table atteinte
+);
+
+  
+  COMPONENT ctrl_i2c_v4_ssm2603 is
+   generic ( c_clk_freq_Hz: integer :=  50_000_000; c_bus_i2c_bps: integer := 100_000);
+    Port (
+           clk_master        : in  STD_LOGIC;                     -- horloge maitre pour le controleur (typique 50 MHz)
+           i_reset           : in  STD_LOGIC;
+           i_stb_read        : in  STD_LOGIC;                     -- demarre un cycle de lecture
+           i_stb_write       : in  STD_LOGIC;                     -- demarre un cycle d ecriture
+           i_adr_reg         : in  std_logic_vector(6 downto 0);  -- adresse registres de configuration
+           i_dat_wreg        : in  std_logic_vector(8 downto 0);  -- 9 bits  -- data registre a transmettre
+           o_dat_rreg        : out std_logic_vector(8 downto 0);  -- 9 bits  -- data registre recue
+           io_sda            : inout std_logic ;
+           io_scl            : inout std_logic ;
+           o_read_req        : out std_logic ;      -- pour tests
+           o_write_req       : out std_logic ;      -- pour tests
+           o_busy            : out std_logic;       -- pour tests
+           o_ack_error       : out   STD_LOGIC;     -- pour tests;
+           o_ena             : out   STD_LOGIC;     -- pour tests;
+           o_rw              : out   STD_LOGIC      -- pour tests;
+                             
+           );
+
+  end COMPONENT;
+
+  component sel_btn_reg
+         port ( clk              : in    std_logic; 
+                i_str_sel_reg    : in    std_logic; 
+                i_reset_sel_reg  : in    std_logic; 
+                o_sel_reg        : out   std_logic_vector (6 downto 0)
+                );
+   end component;
+
+-- Signaux
+----------------------------------------------------------------------------------
+  
+    signal clk_12_288MHz   : std_logic;
+    signal d_strobe_1000Hz : std_logic;
+    signal d_strobe_trame_I2C : std_logic;
+ 
+    signal d_stb_read   : std_logic;
+    signal d_stb_write  : std_logic;
+    signal d_read_req   : std_logic;  -- pour test
+    signal d_write_req  : std_logic;  -- pour test
+   
+    signal d_dat_wreg   : std_logic_vector(8 downto 0);
+    signal d_dat_rreg   : std_logic_vector(8 downto 0);
+    signal d_sclk       : std_logic;
+    signal d_busy       : std_logic;
+    signal d_ack_error  : std_logic;
+    signal d_ena        : std_logic;
+    signal d_rw         : std_logic;
+    
+    signal d_adr_reg    : std_logic_vector(6 downto 0) ;  -- adresse I2c du registre codec
+    signal d_sel_reg    : std_logic_vector(6 downto 0) ;  -- selection registre (directe)
+    signal d_sel_cfg_reg: std_logic_vector(6 downto 0) ;  -- selection registre indirecte par cfg_ssm2603
+    signal q_sel_cfg_reg: std_logic_vector(6 downto 0) ;  -- selection registre indirecte par cfg_ssm2603
+ 
+    signal d_reset_sel_reg : std_logic;
+    signal d_cfg_done      : std_logic;
+    signal d_cfg_busy      : std_logic;
+    
+    signal d_delai_trame_I2C       :  unsigned(7 downto 0); -- delai en nombre de bclk pour configuration
+    constant c_delai_trame_I2C_max :  unsigned(7 downto 0) := "00000110";   --  pour delai 7 ms entre trames I2C
+    signal d_delai_trame_I2C_atteint      : std_logic;
+
+---------------------------------------------------------------------------------------------
+--    init_codec
+---------------------------------------------------------------------------------------------
+begin
+
+ inst_ctrl_i2c: ctrl_i2c_v4_ssm2603
+  generic map (c_clk_freq_Hz => 50_000_000, c_bus_i2c_bps => 100_000 )
+   PORT MAP(
+    clk_master     => clk_p,
+    i_reset        => i_reset,
+    i_stb_read     => d_stb_read,
+    i_stb_write    => d_stb_write,
+    i_adr_reg      => d_adr_reg,
+    i_dat_wreg     => d_dat_wreg,
+    o_dat_rreg     => d_dat_rreg,
+    io_scl         => io_scl ,
+    io_sda         => io_sda,
+    o_ack_error    => d_ack_error,
+    o_ena          =>  d_ena,       -- pour tests
+    o_rw           =>  d_rw,        -- pour tests
+    o_read_req     =>  d_read_req,  -- pour tests
+    o_write_req    =>  d_write_req, -- pour tests
+    o_busy        => d_busy         --
+   );
+   
+   --
+   -- Generation d'un signal de delai entre trames I2C
+   --  version 1
+    compteur_delai_cfg : process (clk_p, i_reset)
+      begin
+         if ( i_reset = '1') then
+             d_delai_trame_I2C <= (others =>'0');
+             d_delai_trame_I2C_atteint <= '0';
+         else
+         if (rising_edge(clk_p) and d_strobe_1000Hz ='1') then
+             d_delai_trame_I2C <= d_delai_trame_I2C + 1;
+             if (d_delai_trame_I2C = c_delai_trame_I2C_max)  then 
+                 d_delai_trame_I2C_atteint <= '1';
+                 d_delai_trame_I2C <= (others =>'0');
+               else
+                d_delai_trame_I2C_atteint <= '0';
+               end if;
+         end if;
+         end if;
+      end process;
+       
+--    --
+--    -- Generation d'un signal de delai entre trames I2C
+--    --
+--     compteur_delai_cfg : process (clk_p, i_reset)
+--       begin
+--          if ( i_reset = '1') then
+--              d_delai_trame_I2C <= (others =>'0');
+--          else
+--          if (rising_edge(clk_p) and d_strobe_1000Hz ='1') then
+--              d_delai_trame_I2C <= d_delai_trame_I2C + 1;
+--              if (d_delai_trame_I2C = c_delai_trame_I2C_max)  then 
+--                  d_delai_trame_I2C <= (others =>'0');
+--              end if;
+--          end if;
+--          end if;
+--       end process;
+       
+--     test_delai_cfg : process (clk_p, i_reset)
+--           begin
+--              if ( i_reset = '1') then
+--                  d_delai_trame_I2C_atteint <= '0';
+--              else
+--              if (rising_edge(clk_p) and d_strobe_1000Hz ='1') then
+--                  if (d_delai_trame_I2C = c_delai_trame_I2C_max)  then 
+--                       d_delai_trame_I2C_atteint <= '1';
+--                    else
+--                       d_delai_trame_I2C_atteint <= '0';
+--                    end if;
+--              end if;
+--              end if;
+--           end process;     
+       
+       
+       
+
+  d_strobe_trame_I2C <= d_strobe_1000Hz and d_delai_trame_I2C_atteint;
+
+  inst_idx_cfg_reg : process (clk_p, i_reset)
+     begin    
+       if   (i_reset = '1') then           
+               d_sel_cfg_reg <= (others =>'0');
+               q_sel_cfg_reg <= (others =>'0');  -- non requis
+               d_cfg_done <= '0';
+         else
+           if rising_edge(clk_p) and (d_strobe_trame_I2C = '1') and (d_cfg_busy  = '1')then
+               if  (d_sel_cfg_reg = "0001011") then     -- limite index = 11 
+             --if  (d_sel_cfg_reg = "0000010") then  -- limite index = 2  -- pour certains test simulation
+                   d_cfg_done <= '1';                   
+                end if;  
+                q_sel_cfg_reg <= d_sel_cfg_reg;     -- valeur courante     
+                d_sel_cfg_reg <= d_sel_cfg_reg + 1; -- prochaine valeur;    
+           end if;
+        end if;
+     end process;
+  
+--inst_busy_cfg_reg 
+inst_busy_cfg_reg : process (clk_p, d_cfg_done )
+    begin
+       if ( d_cfg_done = '1') then
+                d_cfg_busy  <= '0';
+       else
+       if rising_edge(clk_p)  then
+          d_cfg_busy  <= '1';
+        end if;
+        end if;
+    end process;
+
+    d_reset_sel_reg  <= i_reset;
+    o_cfg_done       <= d_cfg_done;
+    o_cfg_busy       <= d_cfg_busy;
+    o_ena            <= d_ena;
+    d_strobe_1000Hz  <= i_strobe_1000Hz;
+    d_stb_read       <= '0';   
+    d_stb_write      <= d_cfg_busy and d_strobe_trame_I2C;
+    d_dat_wreg       <= cfg_ssm2603( to_integer (unsigned(  q_sel_cfg_reg(4 downto 0)  ))) (8 downto 0);
+    d_adr_reg        <= cfg_ssm2603( to_integer (unsigned(  q_sel_cfg_reg(4 downto 0)  ))) (15 downto 9);                                  
+                       
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/mef_cod_i2s_vsb.vhd b/pb_logique_seq.srcs/sources_1/imports/new/mef_cod_i2s_vsb.vhd
new file mode 100644
index 0000000..2357567
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/mef_cod_i2s_vsb.vhd
@@ -0,0 +1,200 @@
+---------------------------------------------------------------------------------------------
+-- circuit mef_cod_i2s_vsb.vhd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 5 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2019.1
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Codeur I2S
+--
+-- notes
+-- frequences (peuvent varier un peu selon les contraintes de mise en oeuvre)
+-- i_lrc        ~ 48.    KHz    (~ 20.8    us)
+-- d_ac_mclk,   ~ 12.288 MHz    (~ 80,715  ns) (non utilisee dans le codeur)
+-- i_bclk       ~ 3,10   MHz    (~ 322,857 ns) freq mclk/4
+-- La durée d'une période reclrc est de 64,5 périodes de bclk ...
+--
+-- Revision  
+-- Revision 14 mai 2019 (version ..._vsb) composants dans entités et fichiers distincts
+---------------------------------------------------------------------------------------------
+-- À faire :
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity mef_cod_i2s_vsb is
+   Port ( 
+   i_bclk      : in std_logic;
+   i_reset     : in    std_logic; 
+   i_lrc       : in std_logic;
+   i_cpt_bits  : in std_logic_vector(6 downto 0);
+ --  
+   o_bit_enable     : out std_logic ;  --
+   o_load_left      : out std_logic ;  --
+   o_load_right     : out std_logic ;  --
+  -- o_str_dat        : out std_logic ;  --  
+   o_cpt_bit_reset  : out std_logic   -- 
+   
+);
+end mef_cod_i2s_vsb;
+
+architecture Behavioral of mef_cod_i2s_vsb is
+  
+-- définition de la MEF de contrôle
+   type fsm_cI2S_etats is (
+         sta_init,
+         sta_g0,
+         sta_g1,
+         sta_g2,
+         sta_g3,
+         sta_gf,
+         sta_d0,
+         sta_d1,
+         sta_d2,
+         sta_d3,
+         sta_df
+         );
+       
+   signal fsm_EtatCourant, fsm_prochainEtat : fsm_cI2S_etats;
+
+begin
+
+   -- Assignation du prochain état
+    process(i_bclk, i_reset)
+    begin
+       if (i_reset ='1') then
+             fsm_EtatCourant <= sta_init;
+       else
+       if rising_edge(i_bclk) then
+             fsm_EtatCourant <= fsm_prochainEtat;
+       end if;
+       end if;
+    end process;
+
+--
+-- conditions de transitions
+transitions: process(i_lrc , fsm_EtatCourant, i_cpt_bits)
+begin
+   case fsm_EtatCourant is
+        when sta_init =>
+            if(i_lrc = '0') then
+                fsm_prochainEtat <= sta_gf;
+            else
+                fsm_prochainEtat <= sta_df;
+            end if;
+         when sta_gf =>
+            if(i_lrc = '0') then
+             fsm_prochainEtat <= sta_gf;
+         else
+             fsm_prochainEtat <= sta_d0;
+         end if;
+         when sta_g0 =>
+             fsm_prochainEtat <= sta_g1;
+         when sta_g1 =>
+            if(   i_cpt_bits = "010111"  ) then
+                fsm_prochainEtat <= sta_g2;
+            else
+                fsm_prochainEtat <= sta_g1;
+            end if;
+         when sta_g2 =>
+            fsm_prochainEtat <= sta_g3;
+         when sta_g3 =>
+            fsm_prochainEtat <= sta_gf;
+ --
+         when sta_df =>
+            if(i_lrc = '0') then
+                 fsm_prochainEtat <= sta_g0;
+              else
+                 fsm_prochainEtat <= sta_df;
+            end if;
+        when sta_d0 =>
+            fsm_prochainEtat <= sta_d1;
+        when sta_d1 =>
+            if(   i_cpt_bits = "010111"  ) then
+                fsm_prochainEtat <= sta_d2;
+            else
+                fsm_prochainEtat <= sta_d1;
+            end if;
+        when sta_d2 =>
+             fsm_prochainEtat <= sta_d3;
+        when sta_d3 =>
+             fsm_prochainEtat <= sta_df;
+     end case;
+  end process;
+
+  -- relations de sorties pour le contrôle du registre et du compteur
+  sortie: process(fsm_EtatCourant, i_lrc )
+  begin
+  
+   case fsm_EtatCourant is
+        when sta_init =>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+       when sta_g0=>
+             o_cpt_bit_reset    <= '1';
+             o_bit_enable     <= '0';
+             o_load_left      <= '0';
+             o_load_right     <= '0';
+        when sta_g1=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '1';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+        when sta_g2=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+        when sta_g3=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+        when sta_gf =>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '1';
+      --
+        when sta_d0=>
+            o_cpt_bit_reset    <= '1';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+         when sta_d1=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '1';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+         when sta_d2=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+        when sta_d3=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '0';
+            o_load_right     <= '0';
+         when sta_df=>
+            o_cpt_bit_reset    <= '0';
+            o_bit_enable     <= '0';
+            o_load_left      <= '1';
+            o_load_right     <= '0';
+     end case;
+    
+    end process;
+  
+end Behavioral;
\ No newline at end of file
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/mef_decod_i2s_v1b.vhd b/pb_logique_seq.srcs/sources_1/imports/new/mef_decod_i2s_v1b.vhd
new file mode 100644
index 0000000..0cd6843
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/mef_decod_i2s_v1b.vhd
@@ -0,0 +1,111 @@
+---------------------------------------------------------------------------------------------
+-- circuit mef_decod_i2s_v1b.vhd                   Version mise en oeuvre avec des compteurs
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 7 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2019.1
+---------------------------------------------------------------------------------------------
+-- Description:
+-- MEF pour decodeur I2S version 1b
+-- La MEF est substituee par un compteur
+--
+-- notes
+-- frequences (peuvent varier un peu selon les contraintes de mise en oeuvre)
+-- i_lrc        ~ 48.    KHz    (~ 20.8    us)
+-- d_ac_mclk,   ~ 12.288 MHz    (~ 80,715  ns) (non utilisee dans le codeur)
+-- i_bclk       ~ 3,10   MHz    (~ 322,857 ns) freq mclk/4
+-- La durée d'une période reclrc est de 64,5 périodes de bclk ...
+--
+-- Revision  
+-- Revision 14 mai 2019 (version ..._v1b) composants dans entités et fichiers distincts
+---------------------------------------------------------------------------------------------
+-- À faire :
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity mef_decod_i2s_v1b is
+   Port ( 
+   i_bclk      : in std_logic;
+   i_reset     : in    std_logic; 
+   i_lrc       : in std_logic;
+   i_cpt_bits  : in std_logic_vector(6 downto 0);
+ --  
+   o_bit_enable     : out std_logic ;  --
+   o_load_left      : out std_logic ;  --
+   o_load_right     : out std_logic ;  --
+   o_str_dat        : out std_logic ;  --  
+   o_cpt_bit_reset  : out std_logic   -- 
+   
+);
+end mef_decod_i2s_v1b;
+
+architecture Behavioral of mef_decod_i2s_v1b is
+
+    signal   d_reclrc_prec  : std_logic ;  --
+    
+begin
+
+   -- pour detecter transitions d_ac_reclrc
+   reglrc_I2S: process ( i_bclk)
+   begin
+   if i_bclk'event and (i_bclk = '1') then
+        d_reclrc_prec <= i_lrc;
+   end if;
+   end process;
+   
+  -- synch compteur codeur
+   rest_cpt: process (i_lrc, d_reclrc_prec, i_reset)
+      begin
+         o_cpt_bit_reset <= (d_reclrc_prec xor i_lrc) or i_reset;
+      end process;
+      
+
+     -- decodage compteur avec case ...   
+        sig_ctrl_I2S:  process (i_cpt_bits, i_lrc )
+            begin
+                case i_cpt_bits is
+                 when "0000000" =>
+                     o_bit_enable     <= '1';
+                     o_load_left      <= '0';
+                     o_load_right     <= '0';
+                     o_str_dat        <= '0';
+                 when   "0000001"  |  "0000010"  |  "0000011"  |  "0000100"  
+                       |  "0000101"  |  "0000110"  |  "0000111"  |  "0001000" 
+                       |  "0001001"  |  "0001010"  |  "0001011"  |  "0001100" 
+                       |  "0001101"  |  "0001110"  |  "0001111"  |  "0010000"  
+                       |  "0010001"  |  "0010010"  |  "0010011"  |  "0010100" 
+                       |  "0010101"  |  "0010110"  |  "0010111"   
+                    =>
+                     o_bit_enable     <= '1';
+                     o_load_left      <= '0';
+                     o_load_right     <= '0';
+                     o_str_dat        <= '0';
+                 when   "0011000"  =>
+                     o_bit_enable     <= '0';
+                     o_load_left      <= not i_lrc;
+                     o_load_right     <=  i_lrc;
+                     o_str_dat        <= '0';
+                 when    "0011001"  =>
+                    o_bit_enable     <= '0';
+                    o_load_left     <= '0';
+                    o_load_right     <= '0';
+                    o_str_dat        <=  i_lrc;
+                 when  others  =>
+                    o_bit_enable     <= '0';
+                    o_load_left      <= '0';
+                    o_load_right     <= '0';
+                    o_str_dat        <= '0';
+                 end case;
+             end process;
+
+     end Behavioral;
\ No newline at end of file
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/module_commande.vhd b/pb_logique_seq.srcs/sources_1/imports/new/module_commande.vhd
new file mode 100644
index 0000000..e36b87f
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/module_commande.vhd
@@ -0,0 +1,68 @@
+--  module_commande.vhd

+--  D. Dalle  30 avril 2019, 16 janv 2020, 23 avril 2020

+--  module qui permet de réunir toutes les commandes (problematique circuit sequentiels)

+--  recues des boutons, avec conditionnement, et des interrupteurs

+

+-- 23 avril 2020 elimination constante mode_seq_bouton: std_logic := '0'

+

+LIBRARY ieee;

+USE ieee.std_logic_1164.all;

+

+entity module_commande IS

+generic (nbtn : integer := 4;  mode_simulation: std_logic := '0');

+    PORT (

+          clk              : in  std_logic;

+          o_reset          : out  std_logic; 

+          i_btn            : in  std_logic_vector (nbtn-1 downto 0); -- signaux directs des boutons

+          i_sw             : in  std_logic_vector (3 downto 0);      -- signaux directs des interrupteurs

+          o_btn_cd         : out std_logic_vector (nbtn-1 downto 0); -- signaux conditionnés 

+          o_selection_fct  :  out std_logic_vector(1 downto 0);

+          o_selection_par  :  out std_logic_vector(1 downto 0)

+          );

+end module_commande;

+

+ARCHITECTURE BEHAVIOR OF module_commande IS

+

+

+component conditionne_btn_v7 is

+generic (nbtn : integer := nbtn;  mode_simul: std_logic := '0');

+    port (

+         CLK          : in std_logic;         -- devrait etre de l ordre de 50 Mhz

+         i_btn        : in    std_logic_vector (nbtn-1 downto 0);

+         --

+         o_btn_db     : out    std_logic_vector (nbtn-1 downto 0);

+         o_strobe_btn : out    std_logic_vector (nbtn-1 downto 0)

+         );

+end component;

+

+

+    signal d_strobe_btn :    std_logic_vector (nbtn-1 downto 0);

+    signal d_btn_cd     :    std_logic_vector (nbtn-1 downto 0); 

+    signal d_reset      :    std_logic;

+   

+BEGIN 

+

+                  

+ inst_cond_btn:  conditionne_btn_v7

+    generic map (nbtn => nbtn, mode_simul => mode_simulation)

+    port map(

+        clk           => clk,

+        i_btn         => i_btn,

+        o_btn_db      => d_btn_cd,

+        o_strobe_btn  => d_strobe_btn  

+         );

+ 

+ process(clk)

+ begin

+    if(rising_edge(clk)) then

+        o_reset <= d_reset;

+    end if;

+ end process;

+ 

+ 

+   o_btn_cd        <= d_btn_cd;

+   o_selection_par <= i_sw(1 downto 0); -- mode de selection du parametre par sw

+   o_selection_fct <= i_sw(3 downto 2); -- mode de selection de la fonction par sw

+   d_reset         <= i_btn(3);         -- pas de contionnement particulier sur reset

+

+END BEHAVIOR;

diff --git a/pb_logique_seq.srcs/sources_1/imports/new/mux2.vhd b/pb_logique_seq.srcs/sources_1/imports/new/mux2.vhd
new file mode 100644
index 0000000..ee18702
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/mux2.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11/23/2021 04:00:46 PM
+-- Design Name: 
+-- Module Name: mux2 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mux2 is
+    Generic ( input_length : integer := 24 );
+    Port ( sel : in STD_LOGIC_VECTOR (1 downto 0);
+           input1 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input2 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           output0 : out STD_LOGIC_VECTOR (input_length-1 downto 0));
+end mux2;
+
+architecture Behavioral of mux2 is
+
+signal tied_to_gnd : std_logic_vector(input_length - 1 downto 0) := (others => '0');
+
+begin
+
+process(sel,input1, input2)
+begin
+  case sel is
+                 when "00" =>
+                     output0 <= tied_to_gnd;
+                 when   "01" =>
+                     output0 <= input1;
+                 when   "10"  =>
+                     output0 <= input2;
+                 when    "11"  =>
+                     output0 <= tied_to_gnd;
+                 when  others  =>
+                     output0 <= tied_to_gnd;
+                 end case;
+end process;
+
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd b/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd
new file mode 100644
index 0000000..4e46dbc
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/mux4.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11/18/2021 11:51:08 AM
+-- Design Name: 
+-- Module Name: mux4 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mux4 is
+    Generic ( input_length : integer := 24 );
+    Port ( input0 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input1 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input2 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           input3 : in STD_LOGIC_VECTOR (input_length-1 downto 0);
+           sel : in STD_LOGIC_VECTOR (1 downto 0);
+           output0 : out STD_LOGIC_VECTOR (input_length-1 downto 0));
+end mux4;
+
+architecture Behavioral of mux4 is
+
+begin
+
+process(sel, input0, input1, input2, input3)
+begin
+  case sel is
+                 when "00" =>
+                     output0 <= input0;
+                 when   "01" =>
+                     output0 <= input1;
+                 when   "10"  =>
+                     output0 <= input2;
+                 when    "11"  =>
+                     output0 <= input3;
+                 when  others  =>
+                     output0 <= input0;
+                 end case;
+end process;
+
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/or2.vhd b/pb_logique_seq.srcs/sources_1/imports/new/or2.vhd
new file mode 100644
index 0000000..b76c01e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/or2.vhd
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11/23/2021 04:00:46 PM
+-- Design Name: 
+-- Module Name: or2 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity or2 is
+    Port ( in1 : in STD_LOGIC;
+           in2 : in STD_LOGIC;
+           output : out STD_LOGIC);
+end or2;
+
+architecture Behavioral of or2 is
+
+begin
+
+output <= in1 or in2;
+
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/reg_24b.vhd b/pb_logique_seq.srcs/sources_1/imports/new/reg_24b.vhd
new file mode 100644
index 0000000..43dd7a9
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/reg_24b.vhd
@@ -0,0 +1,55 @@
+---------------------------------------------------------------------------------------------
+-- circuit reg_24b.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 10 janvier 2019, rev 29 janvier,  2 mai 2019, 5 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Registre de 24 bits
+--
+-- Revision 14 mai 2019 
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- 
+-- 
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity reg_24b is
+  Port ( 
+    i_clk       : in std_logic;
+    i_reset     : in std_logic;
+    i_en        : in std_logic;
+    i_dat       : in std_logic_vector(23 downto 0);
+    o_dat       : out  std_logic_vector(23 downto 0)
+);
+end reg_24b;
+
+architecture Behavioral of reg_24b is
+
+  --
+    signal   q_reg   : std_logic_vector(23 downto 0);   -- registre
+    
+  begin
+  -- registre  
+  reg_dec: process (i_clk, i_reset)
+     begin    
+         if (i_reset = '1')  then
+            q_reg  <= (others =>'0');
+         elsif rising_edge(i_clk) and  (i_en = '1')  then
+            q_reg  <= i_dat;
+        end if;
+     end process;
+ 
+     o_dat   <=  q_reg;
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b.vhd b/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b.vhd
new file mode 100644
index 0000000..1a6e708
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b.vhd
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------------------------
+-- circuit reg_dec_24b.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 15 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Registre à décalages de 24 bits
+--
+-- Revision 14 mai 2019 
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- 
+-- 
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity reg_dec_24b is
+  Port ( 
+    i_clk       : in std_logic;      -- horloge
+    i_reset     : in std_logic;      -- reinitialisation
+    i_load      : in std_logic;      -- activation chargement parallele
+    i_en        : in std_logic;      -- activation decalage
+    i_dat_bit   : in std_logic;      -- entree serie
+    i_dat_load  : in std_logic_vector(23 downto 0);    -- entree parallele
+    o_dat       : out  std_logic_vector(23 downto 0)   -- sortie parallele
+);
+end reg_dec_24b;
+
+architecture Behavioral of reg_dec_24b is
+
+  --
+    signal   q_shift_reg   : std_logic_vector(23 downto 0);   -- registre 
+    
+  begin 
+  -- registre a décalage,  MSB arrive premier, entre par la droite, decalage a gauche  
+  reg_dec: process (i_clk, i_reset)
+     begin    
+       if (i_reset = '1')  then
+          q_shift_reg  <= (others =>'0');
+      elsif rising_edge(i_clk) then  
+                if (i_load = '1')  then
+                   q_shift_reg  <= i_dat_load;
+                elsif (i_en = '1') then
+                   q_shift_reg(23 downto 0) <= q_shift_reg(22 downto 0) & i_dat_bit;
+                end if;
+       end if;
+     end process;
+ 
+     o_dat   <=  q_shift_reg;
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b_fd.vhd b/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b_fd.vhd
new file mode 100644
index 0000000..5a25998
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/reg_dec_24b_fd.vhd
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------------------------
+-- circuit reg_dec_24b_fd.vhd
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- Version         : 1.0
+-- Nomenclature    : 0.8 GRAMS
+-- Date            : 15 mai 2019
+-- Auteur(s)       : Daniel Dalle
+-- Technologies    : FPGA Zynq (carte ZYBO Z7-10 ZYBO Z7-20)
+--
+-- Outils          : vivado 2018.2
+---------------------------------------------------------------------------------------------
+-- Description:
+-- Registre à décalages de 24 bits  : *** fonctionne sur front descendant de l'horloge
+--
+-- Revision 15 mai 2019 
+---------------------------------------------------------------------------------------------
+-- À faire :
+-- 
+-- 
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+entity reg_dec_24b_fd is
+  Port ( 
+    i_clk       : in std_logic;
+    i_reset     : in std_logic;
+    i_load      : in std_logic;
+    i_en        : in std_logic;
+    i_dat_bit   : in std_logic;
+    i_dat_load  : in std_logic_vector(23 downto 0);
+    o_dat       : out  std_logic_vector(23 downto 0)
+);
+end reg_dec_24b_fd;
+
+architecture Behavioral of reg_dec_24b_fd is
+
+  --
+    signal   q_shift_reg   : std_logic_vector(23 downto 0);   -- registre a decalage
+    
+  begin 
+  -- registre a décalage,  MSB arrive premier, entre par la droite, decalage a gauche  
+  reg_dec: process (i_clk, i_reset)
+     begin    
+       if (i_reset = '1')  then
+          q_shift_reg  <= (others =>'0');
+      elsif falling_edge(i_clk) then  
+                if (i_load = '1')  then
+                   q_shift_reg  <= i_dat_load;
+                elsif (i_en = '1') then
+                   q_shift_reg(23 downto 0) <= q_shift_reg(22 downto 0) & i_dat_bit;
+                end if;
+       end if;
+     end process;
+ 
+     o_dat   <=  q_shift_reg;
+
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_3.vhd b/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_3.vhd
new file mode 100644
index 0000000..2e19706
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_3.vhd
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------------------------
+--    sig_fct_3.vhd   (temporaire)
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 29 janvier 2019
+--    Auteur(s)       : 
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2018.2 64 bits
+--
+---------------------------------------------------------------------------------------------
+--  Description 
+--  fonction temporaire, aucun calcul
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+--   À FAIRE:
+--   Voir le guide de la problématique
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
+USE ieee.numeric_std.ALL;
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+---------------------------------------------------------------------------------------------
+--    Description comportementale
+---------------------------------------------------------------------------------------------
+entity sig_fct_3 is
+    Port (  
+    i_ech       : in   std_logic_vector (23 downto 0);
+    o_ech_fct   : out  std_logic_vector (23 downto 0)                                    
+    );
+end sig_fct_3;
+
+----------------------------------------------------------------------------------
+
+architecture Behavioral of sig_fct_3 is
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+    signal d_ech             : std_logic_vector (23 downto 0);   -- 
+    signal d_ech_fct         : std_logic_vector (23 downto 0);   --   
+    signal d_ech_u24         : unsigned (23 downto 0);      --  
+   
+---------------------------------------------------------------------------------------------
+-- 
+begin 
+    -- simple transfert...
+    d_ech_u24   <=  unsigned (i_ech);
+    o_ech_fct   <=  std_logic_vector( d_ech_u24);    
+                 
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_sat_dure.vhd b/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_sat_dure.vhd
new file mode 100644
index 0000000..2c0c463
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/sig_fct_sat_dure.vhd
@@ -0,0 +1,105 @@
+
+---------------------------------------------------------------------------------------------
+--    sig_fct_sat_dure_sol.vhd  
+---------------------------------------------------------------------------------------------YBO
+---------------------------------------------------------------------------------------------
+--    Université de Sherbrooke - Département de GEGI
+--
+--    Version         : 5.0
+--    Nomenclature    : inspiree de la nomenclature 0.2 GRAMS
+--    Date            : 6 mai 2020
+--    Auteur(s)       : Daniel Dalle
+--    Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1) 
+--    Outils          : vivado 2018.2 64 bits
+--
+---------------------------------------------------------------------------------------------
+--    Description 
+--    Module qui applique une saturation au signal d'entrée.
+--    La valeur de saturation est déterminée par c_ech_u24_max.
+--    La fonction de saturation est symétrique pour les valeur positives et négatives.
+--    Le signal est interprété en notation complément a 2
+---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+--    À FAIRE:
+-- 
+---------------------------------------------------------------------------------------------
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+USE ieee.numeric_std.ALL;
+--use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+--use IEEE.std_logic_arith.all;     -- requis pour les constantes telles que cdviv6 etc.
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+----------------------------------------------------------------------------------
+--
+----------------------------------------------------------------------------------
+entity sig_fct_sat_dure is
+generic (c_ech_u24_max : unsigned (23 downto 0) := x"1FFFFF");
+    Port (  
+    i_ech       : in   std_logic_vector (23 downto 0);
+    o_ech_fct   : out  std_logic_vector (23 downto 0)                                    
+    );
+end sig_fct_sat_dure;
+
+----------------------------------------------------------------------------------
+
+architecture Behavioral of sig_fct_sat_dure is
+   
+
+---------------------------------------------------------------------------------
+-- Signaux
+----------------------------------------------------------------------------------
+   
+ --   constant c_ech_u24_max   : unsigned (23 downto 0) := x"7FFFFF" / 4 ;    -- seuil etabli pour test  
+    signal d_ech_u24         : unsigned (23 downto 0);      --  
+    signal d_ech_u24_abs     : unsigned (23 downto 0);      -- 
+    signal d_ech_fct_u24     : unsigned (23 downto 0);      -- 
+    signal d_ech_fct_u24_satur : unsigned (23 downto 0);  -- 
+ 
+    
+---------------------------------------------------------------------------------------------
+--    Description 
+---------------------------------------------------------------------------------------------
+begin 
+    d_ech_u24 <= unsigned (i_ech);
+
+    inst_abs_in: process( d_ech_u24) 
+       begin
+       if (d_ech_u24 = x"800000") then d_ech_u24_abs <= x"7FFFFF"; else
+           if d_ech_u24(23) = '1' then
+                d_ech_u24_abs <= not d_ech_u24 + 1;
+              else
+                d_ech_u24_abs <= d_ech_u24;
+           end if;
+       end if;
+      end process;
+
+    inst_satur: process( d_ech_u24_abs)
+
+       begin
+           if (d_ech_u24_abs > c_ech_u24_max) then
+              d_ech_fct_u24_satur <= c_ech_u24_max; 
+           else 
+              d_ech_fct_u24_satur <= d_ech_u24_abs;
+      end if;
+      end process;
+                  
+    inst_vsign_out: process(d_ech_fct_u24_satur, d_ech_u24)
+     begin
+            if  d_ech_u24(23) = '1' then
+              d_ech_fct_u24 <= not d_ech_fct_u24_satur  + 1;
+              else
+              d_ech_fct_u24 <= d_ech_fct_u24_satur;
+            end if; 
+       end process;
+       
+     o_ech_fct    <= std_logic_vector( d_ech_fct_u24);    
+                 
+end Behavioral;
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/strb_gen_v3.vhd b/pb_logique_seq.srcs/sources_1/imports/new/strb_gen_v3.vhd
new file mode 100644
index 0000000..49d6e56
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/strb_gen_v3.vhd
@@ -0,0 +1,73 @@
+---------------------------------------------------------------------------------------------
+--	str_gen_v3_v3.vhd 
+---------------------------------------------------------------------------------------------
+--	Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+--	Université de Sherbrooke - Département de GEGI
+--	
+--	Version 		: 3.0						révision de la nomenclature
+--	Nomenclature	: ref GRAMS
+--	Date			: 26 mai 2016, 19 juillet 2016, 31 août 2018, 11 septembre 2018, 31 octobre 2018
+--	Auteur(s)		: Daniel Dalle
+--  Technologie     : ZYNQ 7000 PYNQ-Z1 (xc7z020clg400-1) antérieurement sur Artix 7 ( xc7a35tcpg236-1 ) 
+--  Outils          : vivado 2018.2 64 bits
+--	
+--------------------------------
+--	Description
+--------------------------------
+-- Génération de signaux de synchronisation, incluant des "strobes"
+-- 11 septembre 2018: élimination des horloges internes pour réduire le nombre d signaux d'horloges
+--------------------------------
+--	À FAIRE:
+--------------------------------
+--
+--
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity strb_gen is
+
+    Port ( 
+           CLK      : in STD_LOGIC;    -- Entrée  horloge maitre 
+           i_don    : in  STD_LOGIC;   -- signal pour generer strobe au front montant          
+           o_stb    : out  STD_LOGIC   -- strobe synchrone 
+           );    
+                  
+end strb_gen;
+
+architecture Behavioral of strb_gen is
+
+ signal qstrobe : std_logic := '0';
+ signal q_don : std_logic:= '0';
+
+begin
+
+process(CLK, i_don)   -- bascule synchro de l entree
+begin
+	if(CLK'event and CLK = '1') then
+		q_don <= i_don;
+	end if;
+end process;
+
+process(i_don, q_don)   -- sortie impulsion synchrone
+begin
+		o_stb <= i_don and not(q_don);
+end process;
+
+-- autres version pour synchroniser l'entree si necessaire
+--process(CLK, i_don)   -- bascule second niveau
+--begin
+--	if(CLK'event and CLK = '1') then
+--		qq_don <= q_don;
+--	end if;
+--end process;
+
+--process(i_don, q_don, qq_don)   -- sortie impulsion synchrone
+--begin
+--		qstrobe <= q_don and not(qq_don);
+--end process;
+
+end Behavioral;
+
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/synchro_codec_v1.vhd b/pb_logique_seq.srcs/sources_1/imports/new/synchro_codec_v1.vhd
new file mode 100644
index 0000000..ba6041e
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/synchro_codec_v1.vhd
@@ -0,0 +1,158 @@
+---------------------------------------------------------------------------------------------
+--  synchro_codec_v1.vhd 
+---------------------------------------------------------------------------------------------
+--  Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+--  Université de Sherbrooke - Département de GEGI
+--
+--  Version         : 1.0
+--  Nomenclature    : ref GRAMS
+--  Date            : 30 octobre 2018, 7 novembre 2018, 4 janvier 2019, 24 janvier 2019, 10 décembre 2019
+--  Auteur(s)       : Daniel Dalle
+--  Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1)
+--  Outils          : vivado 2018.2 64 bits
+--
+--------------------------------
+--  Description
+--------------------------------
+-- Génération de signaux de synchronisation, incluant des "strobes"
+-- (utilise un PLL)
+-- Ref:
+-- 7 Series Libraries Guide www.xilinx.com 418 UG953 (v2016.3) October 5, 2016
+--   (pages 425 PLLE2_BASE)
+--
+-- revisions
+-- mise a jour D Dalle 10 decembre 2019  v1 synchro_zybo_v1 nomenclature synchro_demo_codec_v4 devient synchro_zybo_v1
+-- mise a jour D Dalle 24 janvier 2019   v4 strobe commentaires, élimination entrée reset
+-- mise a jour D Dalle 7  janvier 2019   v3 strobe 1000Hz   validation / correction S_1Hz
+-- mise a jour D Dalle 4  janvier 2019   v3 strobe 1000Hz
+-- mise a jour D Dalle 27 decembre 2018  v3 tous les strobes sur 50 MHz
+-- mise a jour D Dalle 17 decembre 2018 constantes horloges en Hz (pour coherence avec autres modules)
+---------------------------------------------------------------------------------------------
+--  À FAIRE:
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity synchro_codec_v1 is
+generic (cst_CLK_syst_Hz: integer := 100_000_000); -- valeur par defaut fréquence de clkm
+    Port (
+    sysclk       : in STD_LOGIC;    -- Entrée  horloge système  
+                                    -- (typique 125 MHz (1/8 ns) ou 100  ( 1/10 ns))
+    o_clk_0      : out  STD_LOGIC;  -- horloge via bufg 50 MHz  (20 ns)  
+                                    ---  (sera pour clk_p, horloge)
+    o_mclk       : out  STD_LOGIC;  -- horloge via bufg 12.389 MHz 
+                                    -- (80,714 ns) (pour codec)
+    o_stb_1000Hz : out  STD_LOGIC;  -- strobe durée 1/o_clk_0 sync sur 1000Hz
+    o_stb_1Hz    : out  STD_LOGIC;  -- strobe durée 1/o_clk_0 sync sur  1Hz
+    o_S_1Hz      : out  STD_LOGIC;  -- Signal temoin 1 Hz
+    o_bclk       : out  STD_LOGIC;  -- horloge bit clk 
+                                    -- (~ 12.289 MHz/4 soit 3,07225 MHz (325.49 ns) )
+    o_reclrc     : out  STD_LOGIC   -- horloge record, play back, 
+                                    -- sampling rate clock, left right channel 
+                                    -- (~ 48 KHz (20,83 us))
+    );
+end synchro_codec_v1;
+
+
+
+
+architecture Behavioral of synchro_codec_v1 is
+
+  component synchro_zybo_v1 is
+   generic (const_CLK_syst_Hz: integer := 100_000_000);  -- valeur par defaut de fréquence de clkm
+       Port (
+              sysclk         : in STD_LOGIC;    -- Entrée  horloge maitre  (typique 125 MHz (1/8 ns) ou 100  ( 1/10 ns))
+              o_clk_0      : out  STD_LOGIC;  -- horloge via bufg 50.    MHz  (20 ns)
+              o_clk_1      : out  STD_LOGIC;  -- horloge via bufg 12.389 MHz  (80,714 ns)
+              o_stb_1000Hz : out  STD_LOGIC;  -- strobe durée 1/o_clk_0 sync sur 1000Hz
+              o_stb_1Hz    : out  STD_LOGIC;  -- strobe durée 1/o_clk_0 sync sur  1Hz
+              o_S_1Hz      : out  STD_LOGIC   -- Signal temoin 1 Hz
+              );
+   end component;
+
+   component gen_clk_codec
+      port  (
+              i_rst     : in STD_LOGIC;     -- entree reset
+              m_clk     : in STD_LOGIC;     -- Entrée  horloge maitre codec  (defaut 12.289 MHz  (81.374 ns) )
+              o_bclk    : out  STD_LOGIC;   -- horloge bit clk (defaut 12.289 MHz / 4 soit 3,07225 MHz  (325.49 ns) )
+              o_reclrc  : out  STD_LOGIC    -- horloge record, play back, sampling rate clock, left right channel (defaut 48 KHz (20,83 us))
+             );
+    end component;
+
+--   component strb_gen is
+--         Port (
+--                CLK      : in STD_LOGIC;     -- Entrée  horloge maitre
+--                i_don    : in  STD_LOGIC;   -- signal pour generer strobe au front montant
+--                o_stb    : out  STD_LOGIC   -- strobe synchrone
+--                );
+--     end component;
+
+   signal sysclk_int : std_logic;
+   signal clk_0_int   : std_logic;
+   signal clk_1_int   : std_logic;
+
+   signal d_strobe_1000Hz_int : std_logic;
+   signal d_strobe_1Hz_int    : std_logic;
+   signal d_S1Hz_int    : std_logic;
+   signal d_bclk_int : std_logic;
+   signal d_lrc_int    : std_logic;
+   signal d_T1Hz          : std_logic;
+   -- signal reset           : std_logic;
+
+begin
+
+ inst_synchro : synchro_zybo_v1
+  generic map (const_CLK_syst_Hz => cst_CLK_syst_Hz)
+     port map (
+      sysclk            => sysclk_int,
+      o_clk_0           => clk_0_int,      -- 50 MHz
+      o_clk_1           => clk_1_int,      -- master clk pour SSM2603
+      o_stb_1000Hz      => d_strobe_1000Hz_int,
+      o_stb_1Hz         => d_strobe_1Hz_int,
+      o_S_1Hz           => d_S1Hz_int
+      );
+
+  -- generateur horloge echantillonnage (ADC sampling Rate) et transfert binaire
+  inst_gen_clk_codec : gen_clk_codec
+     Port map (
+          i_rst     => '0',
+          m_clk     => clk_1_int,
+          o_bclk    => d_bclk_int,
+          o_reclrc  => d_lrc_int
+       );
+
+---- Outils développement du code
+----  buffer horloge 
+--ClockBuf0: bufg
+--port map(
+--  I   => CLKOUT0,
+--  O   => clk_0_interne
+--  );
+--o_clk_0  <= clk_0_interne ; --
+
+--ClockBufer1: bufg
+--    port map(
+--        I    => CLKOUT1,
+--        O    => clk_1_interne
+--        );
+
+sysclk_int   <= sysclk ; --
+o_clk_0      <= clk_0_int ; --
+o_mclk       <= clk_1_int ; --
+o_S_1Hz      <= d_S1Hz_int;
+o_stb_1000Hz <= d_strobe_1000Hz_int;
+o_stb_1Hz    <= d_strobe_1Hz_int;
+
+o_bclk    <= d_bclk_int;
+o_reclrc    <= d_lrc_int;
+
+
+end Behavioral;
+
diff --git a/pb_logique_seq.srcs/sources_1/imports/new/synchro_zybo_v1.vhd b/pb_logique_seq.srcs/sources_1/imports/new/synchro_zybo_v1.vhd
new file mode 100644
index 0000000..7feeaac
--- /dev/null
+++ b/pb_logique_seq.srcs/sources_1/imports/new/synchro_zybo_v1.vhd
@@ -0,0 +1,266 @@
+---------------------------------------------------------------------------------------------
+-- synchro_zybo_v1.vhd
+---------------------------------------------------------------------------------------------
+-- Generation d'horloge et de signaux de synchronisation
+---------------------------------------------------------------------------------------------
+-- Université de Sherbrooke - Département de GEGI
+-- 
+-- Version          : 1.0
+-- Nomenclature     : ref GRAMS
+-- Date             : 30 octobre 2018, 7 novembre 2018, 4 janvier 2019, 24 janvier 2019
+-- Auteur(s)        : Daniel Dalle
+--  Technologie     : ZYNQ 7000 Zybo Z7-10 (xc7z010clg400-1)
+--  Outils          : vivado 2018.2 64 bits
+-- 
+--------------------------------
+-- Description
+--------------------------------
+-- Génération de signaux de synchronisation, incluant des "strobes"
+-- (utilise un PLL)
+-- Ref:
+-- 7 Series Libraries Guide www.xilinx.com 418 UG953 (v2016.3) October 5, 2016
+--   (pages 425 PLLE2_BASE)
+--
+-- revisions
+-- mise a jour D Dalle 17 octobre 2019   nomenclature synchro_demo_codec_v4 devient synchro_zybo_v1
+-- mise a jour D Dalle 24 janvier 2019   v4 strobe commentaires, élimination entrée reset
+-- mise a jour D Dalle 7  janvier 2019   v3 strobe 1000Hz   validation / correction S_1Hz
+-- mise a jour D Dalle 4  janvier 2019   v3 strobe 1000Hz   
+-- mise a jour D Dalle 27 decembre 2018  v3 tous les strobes sur 50 MHz  
+-- mise a jour D Dalle 17 decembre 2018 constantes horloges en Hz (pour coherence avec autres modules)
+---------------------------------------------------------------------------------------------
+-- À FAIRE:
+---------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.all;     -- requis pour les constantes  etc.
+use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- pour les additions dans les compteurs
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity synchro_zybo_v1 is
+generic (const_CLK_syst_Hz: integer := 100_000_000); -- valeur par defaut fréquence de clkm
+Port ( 
+   sysclk      : in  STD_LOGIC; -- Entrée horloge maitre, typique 100 MHz (10 ns) ou 125 (8 ns)
+   o_clk_0     : out STD_LOGIC; -- horloge via bufg 50.    MHz  (20 ns) 
+   o_clk_1     : out STD_LOGIC; -- horloge via bufg 12.389 MHz  (80,714 ns)
+   o_stb_1000Hz: out STD_LOGIC; -- strobe durée 1/o_clk_0 sync sur 1000Hz
+   o_stb_1Hz   : out STD_LOGIC; -- strobe durée 1/o_clk_0 sync sur  1Hz
+   o_S_1Hz     : out STD_LOGIC  -- Signal temoin 1 Hz
+   );                   
+end synchro_zybo_v1;
+
+
+architecture Behavioral of synchro_zybo_v1 is
+
+   component strb_gen is
+         Port ( 
+                CLK      : in STD_LOGIC;     -- Entrée  horloge maitre 
+                i_don    : in  STD_LOGIC;   -- signal pour generer strobe au front montant          
+                o_stb    : out  STD_LOGIC   -- strobe synchrone 
+                );                          
+     end component;
+ 
+-- parametres pour constantes du PLL                                                          -- sim 125 MHz sysclk
+ constant const_CLK_syst_MHz : integer := integer( real (const_CLK_syst_Hz) / 1000000.0);     -- verif 125
+ constant c_CLKFBOUT_MULT    : integer := 56; -- Multiply value for all CLKOUT, (2-64)
+ constant c_CLKIN1_PERIOD    : real := 1000.0 / real(const_CLK_syst_MHz) ;  -- Input clock period in ns to ps resolution 
+                                                                            -- (i.e. 33.333 is 30 MHz).
+-- constant c_DIVCLK_DIVIDE  : integer := 7;   -- Master division value, (1-56)
+ constant c_DIVCLK_DIVIDE    : integer := 5;   -- Master division value, (1-56)
+ -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
+ constant c_CLKOUT0_DIVIDE : integer := const_CLK_syst_MHz*c_CLKFBOUT_MULT/c_DIVCLK_DIVIDE/50 ; -- pour obtenir 50 MHz
+                                                                                                -- verif 28
+ constant c_CLKOUT1_DIVIDE : integer := const_CLK_syst_MHz*c_CLKFBOUT_MULT*1000/c_DIVCLK_DIVIDE/12289; -- pour obtenir 12.289 MHz
+                                                                                                -- verif 113
+ 
+  constant FRQ_exact_KHz : integer := 1000*const_CLK_syst_MHz*c_CLKFBOUT_MULT/c_DIVCLK_DIVIDE/c_CLKOUT0_DIVIDE ;
+   -- calcul des constantes avec CLKOUT1 comme fréquence de base (12,2888 MHz)  **   CLKOUT1 CLKOUT1 CLKOUT1 CLKOUT1
+                                                                                       -- verif 50_000
+  constant FRQ_niv1_KHz_des :       integer := 200 ; -- KHz (clk intermediaire desiree pour compteurs)
+                                                                                       -- verif 200
+  constant ctmp1:  integer  :=(FRQ_exact_KHz/(FRQ_niv1_KHz_des)-1);  
+                                                                                       -- verif 249 ( = x"0F9")
+  constant cdiv1 : std_logic_vector(11  downto 0):= conv_std_logic_vector(ctmp1, 12); 
+                                                                                       -- verif x"0F9"
+  constant FRQ_niv1_KHz_exact : integer := FRQ_exact_KHz / ctmp1;
+
+  constant FRQ_niv2_Hz_des :       integer := 2000 ; -- Hz (frq toggle intermediaire desiree )       --- **** valeur v3 modifiee
+ -- constant ctmp2:  integer  :=(1000*FRQ_niv1_KHz_exact/(2*FRQ_niv2_Hz_des)-1);  -- calcul avec toggle
+                                                                                              
+  constant ctmp2:  integer  :=(1000*FRQ_niv1_KHz_exact/(FRQ_niv2_Hz_des)-1);  -- 
+                                                                                      -- verif 99
+  constant cdiv2 : std_logic_vector(11  downto 0):= conv_std_logic_vector(ctmp2, 12); -- 
+  constant FRQ_niv2_Hz_exact : integer := 1000*FRQ_niv1_KHz_exact / (ctmp2);
+                                                                                      -- verif 2020 
+  --  
+  constant FRQ_inter_3_Hz_des :       integer := 1 ; -- Hz (clk  desiree )
+  constant ctmp3:  integer  :=(FRQ_niv2_Hz_exact/(2*FRQ_inter_3_Hz_des)-1);  
+                                                                                      -- verif 1009 (= x"3F1")
+  --constant ctmp3:  integer  :=(FRQ_niv2_Hz_exact/(FRQ_inter_3_Hz_des)-1); 
+                                                                                             
+  constant cdiv3 : std_logic_vector(11  downto 0):= conv_std_logic_vector(ctmp3, 12); 
+
+ signal ValueCounter1      : std_logic_vector(11 downto 0)   := (others => '0');
+ signal ValueCounter2      : std_logic_vector(11 downto 0)   := (others => '0');
+ signal ValueCounter3      : std_logic_vector(11 downto 0)  := (others => '0');
+
+ signal d_TC_ValueCounter1Hz : std_logic := '0';
+
+ signal clk_0_interne      : std_logic := '0';
+ signal clk_1_interne      : std_logic := '0';
+ signal d_s1HzInt          : std_logic := '0' ;
+ signal q_s1HzInt          : std_logic := '0' ;
+ --signal d_200kHzInt   : std_logic := '0' ;
+ signal d_s1000HzInt       : std_logic := '0' ;
+-- signal q_s100HzInt       : std_logic := '0' ;
+-- signal qq_s100HzInt       : std_logic := '0' ;
+ signal d_strobe_1000HzInt : std_logic := '0' ;
+ signal d_strobe_1HzInt    : std_logic := '0' ;
+ 
+ signal CLKOUT0 : std_logic := '0' ;
+ signal CLKOUT1 : std_logic := '0' ; 
+ signal CLKOUT2 : std_logic := '0' ; -- non utilisee
+ signal CLKOUT3 : std_logic := '0' ; -- non utilisee
+ signal CLKOUT4 : std_logic := '0' ; -- non utilisee
+ signal CLKOUT5 : std_logic := '0' ; -- non utilisee
+
+ signal CLKFBOUT : std_logic;     -- 1-bit output: Feedback clock
+ signal LOCKED   : std_logic;     -- 1-bit output: LOCK
+ signal clk_in   : std_logic;     -- 1-bit input: Input clock 
+
+
+begin
+
+PLLE2_BASE_inst : PLLE2_BASE
+ generic map (
+ BANDWIDTH => "OPTIMIZED",  -- OPTIMIZED, HIGH, LOW
+ CLKFBOUT_MULT  => c_CLKFBOUT_MULT,       -- Multiply value for all CLKOUT, (2-64)
+ CLKFBOUT_PHASE => 0.0,     -- Phase offset in degrees of CLKFB, (-360.000-360.000).
+ CLKIN1_PERIOD  => c_CLKIN1_PERIOD,     -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
+ -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
+ CLKOUT0_DIVIDE => c_CLKOUT0_DIVIDE,
+ CLKOUT1_DIVIDE => c_CLKOUT1_DIVIDE,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT5_DIVIDE => 1,
+ -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
+ CLKOUT0_DUTY_CYCLE => 0.5,
+ CLKOUT1_DUTY_CYCLE => 0.5,
+ CLKOUT2_DUTY_CYCLE => 0.5,
+ CLKOUT3_DUTY_CYCLE => 0.5,
+ CLKOUT4_DUTY_CYCLE => 0.5,
+ CLKOUT5_DUTY_CYCLE => 0.5,
+ -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
+ CLKOUT0_PHASE => 0.0,
+ CLKOUT1_PHASE => 0.0,
+ CLKOUT2_PHASE => 0.0,
+ CLKOUT3_PHASE => 0.0,
+ CLKOUT4_PHASE => 0.0,
+ CLKOUT5_PHASE => 0.0,
+ DIVCLK_DIVIDE => c_DIVCLK_DIVIDE, -- Master division value, (1-56)
+ REF_JITTER1   => 0.01, -- Reference input jitter in UI, (0.000-0.999).
+ STARTUP_WAIT  => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
+ )
+ port map (
+-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
+CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
+CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
+CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
+CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
+CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
+CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
+-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
+CLKFBOUT => CLKFBOUT,     -- 1-bit output: Feedback clock
+LOCKED => LOCKED,         -- 1-bit output: LOCK
+CLKIN1 => sysclk,         -- 1-bit input: Input clock
+-- Control Ports: 1-bit (each) input: PLL control ports
+PWRDWN => '0',       -- 1-bit input: Power-down
+--RST => i_rst, -- 1-bit input: Reset
+RST =>'0', -- 1-bit input: Reset
+-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
+CLKFBIN => CLKFBOUT      -- 1-bit input: Feedback clock
+ );
+ 
+--  buffer horloge 
+ClockBuf0: bufg
+port map(
+   I  => CLKOUT0,
+   O  => clk_0_interne
+   ); 
+o_clk_0  <= clk_0_interne ; -- 
+                          
+ClockBufer1: bufg
+    port map(
+        I    => CLKOUT1,
+        O    => clk_1_interne
+        );
+
+o_clk_1      <= clk_1_interne ; --     
+o_S_1Hz      <= d_s1HzInt;
+o_stb_1000Hz <= d_strobe_1000HzInt;
+o_stb_1Hz    <= d_strobe_1HzInt;
+
+-- gestion des compteurs  (estimes de durees calcules pour sysclk = 125 MHz) --V3
+process(clk_0_interne)           -- avec 50 MHz
+--
+begin                                                     -- Estimation avec clk1 = 12,288 
+                                                          --     (12,389 selon calcul avec sysclk =125 MHz)
+                                                          --
+   if(clk_0_interne'event and clk_0_interne = '1') then   -- evenement se produit aux 81 ns approx
+       ValueCounter1 <= ValueCounter1 + 1;
+       if (ValueCounter1 = cdiv1) then                    -- evenement se produit aux 5 us approx
+            ValueCounter1 <= "000000000000"; 
+            ValueCounter2 <= ValueCounter2 + 1;
+            if (ValueCounter2 = cdiv2) then
+               d_s1000HzInt <= Not d_s1000HzInt;           -- evenement se produit aux 500 us approx (2 KHz)
+               ValueCounter2 <= "000000000000";            -- la periode de d_s1000HzInt est alors ~ 1 ms
+               ValueCounter3 <= ValueCounter3 + 1;
+               if (ValueCounter3 = cdiv3) then             -- evenement se produit aux 500 ms approx (2 Hz)
+                   ValueCounter3 <= "000000000000";
+                     d_s1HzInt <= Not d_s1HzInt;           -- ici on fait un toggle donc 2*500 ms  
+                                                           --     -> 1 sec.  pour frequence de d_s1HzInt;
+               end if;
+            end if;                 
+      end if;
+   end if;
+end process;
+
+
+
+inst_strb_1000Hz : strb_gen 
+     -- les strobes sont synchronisés sur l'horloge clk_1_interne
+         Port map ( 
+                CLK     =>  clk_0_interne,
+                i_don   =>  d_s1000HzInt,     
+                o_stb   =>  d_strobe_1000HzInt
+                ); 
+ 
+inst_strb_1Hz : strb_gen 
+     -- les strobes sont synchronisés sur l'horloge clk_1_interne
+         Port map ( 
+                CLK     =>  clk_0_interne,
+                i_don   =>  d_s1HzInt,     
+                o_stb   =>  d_strobe_1HzInt
+                );                          
+                 
+
+--process(CLKOUT1, q_s100HzInt)   -- bascule synchro de l entree
+--begin
+-- if(CLKOUT1'event and CLKOUT1 = '1') then
+--     qq_s100HzInt <= q_s100HzInt;
+-- end if;
+--end process;
+
+--process(q_s100HzInt, qq_s100HzInt)   -- sortie impulsion synchrone
+--begin
+--    d_strobe_100HzInt <= q_s100HzInt and not(qq_s100HzInt);
+--end process;
+
+
+end Behavioral;
+
diff --git a/pb_logique_seq.xpr b/pb_logique_seq.xpr
new file mode 100644
index 0000000..0223e17
--- /dev/null
+++ b/pb_logique_seq.xpr
@@ -0,0 +1,1080 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="54" Path="/home/master/Dropbox/A/scholar/sherbrooke/25-05-S4/app2/problematique/pb_logique_seq.xpr">
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+  <Configuration>
+    <Option Name="Id" Val="ae302d5aa3284400815652c101d33dae"/>
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+    <Option Name="CompiledLibDirXSim" Val=""/>
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+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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+    </Run>
+    <Run Id="design_1_mef_cod_i2s_vsb_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_mef_cod_i2s_vsb_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mef_cod_i2s_vsb_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_mef_cod_i2s_vsb_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_util_vector_logic_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_util_vector_logic_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_util_vector_logic_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_util_vector_logic_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_calcul_param_3_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_calcul_param_3_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_calcul_param_3_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_calcul_param_3_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_reg_dec_24b_fd_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_reg_dec_24b_fd_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_reg_dec_24b_fd_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_reg_dec_24b_fd_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_sig_fct_3_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_sig_fct_3_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_sig_fct_3_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_sig_fct_3_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_mux2_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_mux2_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mux2_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_mux2_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_affhexPmodSSD_v3_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_affhexPmodSSD_v3_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_affhexPmodSSD_v3_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_affhexPmodSSD_v3_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_sig_fct_sat_dure_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_sig_fct_sat_dure_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_sig_fct_sat_dure_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_sig_fct_sat_dure_0_1_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_sig_fct_sat_dure_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_sig_fct_sat_dure_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_sig_fct_sat_dure_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_sig_fct_sat_dure_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_compteur_nbits_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_compteur_nbits_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_compteur_nbits_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_compteur_nbits_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_mef_decod_i2s_v1b_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_mef_decod_i2s_v1b_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_mef_decod_i2s_v1b_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_mef_decod_i2s_v1b_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_reg_24b_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_reg_24b_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_reg_24b_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_reg_24b_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="design_1_reg_24b_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_reg_24b_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_reg_24b_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../../C:/Users/rosj2103/Downloads/pb_logique_seq/pb_logique_seq.srcs/utils_1/imports/design_1_reg_24b_0_1_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/rightInput.txt b/rightInput.txt
new file mode 100644
index 0000000..0dcaa29
--- /dev/null
+++ b/rightInput.txt
@@ -0,0 +1,48 @@
+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+5FFFFF

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001

+A00001
\ No newline at end of file
diff --git a/schema.tcl b/schema.tcl
new file mode 100644
index 0000000..b7ba6b3
--- /dev/null
+++ b/schema.tcl
@@ -0,0 +1,43 @@
+highlight_objects [get_bd_cells M5_parametre_1] -color red

+highlight_objects [get_bd_cells M6_parametre_2] -color red

+highlight_objects [get_bd_cells M8_commande] -color red

+highlight_objects [get_bd_cells M1_decodeur_i2s/MEF_decodeur_i2s] -color red

+

+

+set curDir [get_property DIRECTORY [current_project]]

+

+

+set_property location {1 178 353} [get_bd_cells M1_decodeur_i2s]

+set_property location {2 448 219} [get_bd_cells M2_fonction_distortion_dure1]

+set_property location {2 434 305} [get_bd_cells M3_fonction_distorsion_dure2]

+set_property location {2 410 384} [get_bd_cells M4_fonction3]

+set_property location {2.5 737 268} [get_bd_cells Multiplexeur_choix_fonction]

+set_property location {1 139 570} [get_bd_cells M9_codeur_i2s]

+set_property location {2 429 734} [get_bd_cells M8_commande]

+set_property location {3.5 1059 166} [get_bd_cells M5_parametre_1]

+set_property location {4 1057 59} [get_bd_cells parametre_0]

+set_property location {4 1026 341} [get_bd_cells M6_parametre_2]

+set_property location {4 1070 477} [get_bd_cells M7_parametre_3]

+set_property location {4.5 1369 284} [get_bd_cells Multiplexeur_choix_parametre]

+set_property location {5.5 1637 268} [get_bd_cells M10_conversion_affichage]

+set_property location {-72 570} [get_bd_ports o_pbdat]

+set_property location {-134 728} [get_bd_ports i_btn]

+set_property location {-116 750} [get_bd_ports i_sw]

+set_property location {-89 380} [get_bd_ports clk_100MHz]

+set_property location {-95 357} [get_bd_ports i_lrc]

+set_property location {-96 341} [get_bd_ports i_recdat]

+set_property location {2130 272} [get_bd_ports JPmod]

+set_property location {2130 120} [get_bd_ports o_param]

+set_property location {2130 700} [get_bd_ports o_sel_fct]

+set_property location {2130 725} [get_bd_ports o_sel_par]

+

+

+set_property USER_COMMENTS.comment_1 {Modules à modifier:

+MEF_decodeur_i2s (dans M1_decodeur_i2s)

+M5_parametre_1

+M6_parametre_2

+M8_commande

+Pour plus de clarté, vous pouvez cacher les fils pour les horloges

+et les resets dans les paramètres (engrenage en haut a droite de cette fenêtre).

+} [current_bd_design]

+